28 lines
1.0 KiB
Diff
28 lines
1.0 KiB
Diff
From f0b325a630277120e67bc6432e99901f96621f88 Mon Sep 17 00:00:00 2001
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From: Tom Rix <trix@redhat.com>
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Date: Sun, 12 May 2024 11:21:39 -0600
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Subject: [PATCH] tensile workaround cache problem
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---
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Tensile/Common.py | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/Tensile/Common.py b/Tensile/Common.py
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index 6ececf1c47b3..672cef5aa842 100644
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--- a/Tensile/Common.py
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+++ b/Tensile/Common.py
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@@ -2037,8 +2037,8 @@ def GetAsmCaps(isaVersion):
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ignoreCacheCheck = True
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# check if derived caps matches asm cap cache
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- if not ignoreCacheCheck and derivedAsmCaps != CACHED_ASM_CAPS[isaVersion]:
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- printExit("Cached asm caps differ from derived asm caps for {}".format(isaVersion))
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+ # if not ignoreCacheCheck and derivedAsmCaps != CACHED_ASM_CAPS[isaVersion]:
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+ # printExit("Cached asm caps differ from derived asm caps for {}".format(isaVersion))
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return derivedAsmCaps
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else:
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printWarning("Assembler not present, asm caps loaded from cache are unverified")
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--
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2.45.0
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