88 lines
3.3 KiB
Diff
88 lines
3.3 KiB
Diff
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# Commit fa4d026737a47cd1d66ffb797a29150b4453aa9f
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# Date 2024-06-18 15:12:44 +0200
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# Author Jan Beulich <jbeulich@suse.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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x86/Intel: unlock CPUID earlier for the BSP
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Intel CPUs have a MSR bit to limit CPUID enumeration to leaf two. If
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this bit is set by the BIOS then CPUID evaluation does not work when
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data from any leaf greater than two is needed; early_cpu_init() in
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particular wants to collect leaf 7 data.
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Cure this by unlocking CPUID right before evaluating anything which
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depends on the maximum CPUID leaf being greater than two.
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Inspired by (and description cloned from) Linux commit 0c2f6d04619e
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("x86/topology/intel: Unlock CPUID before evaluating anything").
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
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--- a/xen/arch/x86/cpu/common.c
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+++ b/xen/arch/x86/cpu/common.c
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@@ -336,7 +336,8 @@ void __init early_cpu_init(bool verbose)
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c->x86_vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx);
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switch (c->x86_vendor) {
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- case X86_VENDOR_INTEL: actual_cpu = intel_cpu_dev; break;
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+ case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c);
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+ actual_cpu = intel_cpu_dev; break;
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case X86_VENDOR_AMD: actual_cpu = amd_cpu_dev; break;
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case X86_VENDOR_CENTAUR: actual_cpu = centaur_cpu_dev; break;
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case X86_VENDOR_SHANGHAI: actual_cpu = shanghai_cpu_dev; break;
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--- a/xen/arch/x86/cpu/cpu.h
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+++ b/xen/arch/x86/cpu/cpu.h
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@@ -24,3 +24,5 @@ void amd_init_lfence(struct cpuinfo_x86
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void amd_init_ssbd(const struct cpuinfo_x86 *c);
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void amd_init_spectral_chicken(void);
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void detect_zen2_null_seg_behaviour(void);
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+
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+void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c);
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--- a/xen/arch/x86/cpu/intel.c
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+++ b/xen/arch/x86/cpu/intel.c
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@@ -303,10 +303,24 @@ static void __init noinline intel_init_l
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ctxt_switch_masking = intel_ctxt_switch_masking;
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}
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-static void cf_check early_init_intel(struct cpuinfo_x86 *c)
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+/* Unmask CPUID levels if masked. */
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+void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c)
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{
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- u64 misc_enable, disable;
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+ uint64_t misc_enable, disable;
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+
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+ rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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+
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+ disable = misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
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+ if (disable) {
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+ wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
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+ bootsym(trampoline_misc_enable_off) |= disable;
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+ c->cpuid_level = cpuid_eax(0);
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+ printk(KERN_INFO "revised cpuid level: %u\n", c->cpuid_level);
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+ }
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+}
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+static void cf_check early_init_intel(struct cpuinfo_x86 *c)
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+{
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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c->x86_cache_alignment = 128;
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@@ -315,16 +329,7 @@ static void cf_check early_init_intel(st
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bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DISABLE)
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printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n");
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- /* Unmask CPUID levels and NX if masked: */
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- rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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-
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- disable = misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
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- if (disable) {
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- wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
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- bootsym(trampoline_misc_enable_off) |= disable;
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- printk(KERN_INFO "revised cpuid level: %d\n",
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- cpuid_eax(0));
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- }
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+ intel_unlock_cpuid_leaves(c);
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/* CPUID workaround for Intel 0F33/0F34 CPU */
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if (boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 3 &&
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