66 lines
2.0 KiB
Diff
66 lines
2.0 KiB
Diff
# Commit 9e6dbbe8bf400aacb99009ddffa91d2a0c312b39
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# Date 2024-06-19 13:00:06 +0100
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# Author Andrew Cooper <andrew.cooper3@citrix.com>
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# Committer Andrew Cooper <andrew.cooper3@citrix.com>
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x86/xstate: Fix initialisation of XSS cache
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The clobbering of this_cpu(xcr0) and this_cpu(xss) to architecturally invalid
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values is to force the subsequent set_xcr0() and set_msr_xss() to reload the
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hardware register.
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While XCR0 is reloaded in xstate_init(), MSR_XSS isn't. This causes
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get_msr_xss() to return the invalid value, and logic of the form:
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old = get_msr_xss();
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set_msr_xss(new);
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...
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set_msr_xss(old);
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to try and restore said invalid value.
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The architecturally invalid value must be purged from the cache, meaning the
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hardware register must be written at least once. This in turn highlights that
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the invalid value must only be used in the case that the hardware register is
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available.
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Fixes: f7f4a523927f ("x86/xstate: reset cached register values on resume")
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/xstate.c
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+++ b/xen/arch/x86/xstate.c
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@@ -641,13 +641,6 @@ void xstate_init(struct cpuinfo_x86 *c)
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return;
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}
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- /*
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- * Zap the cached values to make set_xcr0() and set_msr_xss() really
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- * write it.
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- */
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- this_cpu(xcr0) = 0;
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- this_cpu(xss) = ~0;
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-
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cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
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feature_mask = (((u64)edx << 32) | eax) & XCNTXT_MASK;
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BUG_ON(!valid_xcr0(feature_mask));
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@@ -657,8 +650,19 @@ void xstate_init(struct cpuinfo_x86 *c)
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* Set CR4_OSXSAVE and run "cpuid" to get xsave_cntxt_size.
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*/
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set_in_cr4(X86_CR4_OSXSAVE);
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+
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+ /*
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+ * Zap the cached values to make set_xcr0() and set_msr_xss() really write
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+ * the hardware register.
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+ */
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+ this_cpu(xcr0) = 0;
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if ( !set_xcr0(feature_mask) )
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BUG();
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+ if ( cpu_has_xsaves )
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+ {
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+ this_cpu(xss) = ~0;
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+ set_msr_xss(0);
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+ }
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if ( bsp )
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{
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