104 lines
4.9 KiB
Diff
104 lines
4.9 KiB
Diff
# Commit 87f37449d586b4d407b75235bb0a171e018e25ec
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# Date 2023-11-02 10:50:59 +0100
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# Author Roger Pau Monné <roger.pau@citrix.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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x86/i8259: do not assume interrupts always target CPU0
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Sporadically we have seen the following during AP bringup on AMD platforms
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only:
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microcode: CPU59 updated from revision 0x830107a to 0x830107a, date = 2023-05-17
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microcode: CPU60 updated from revision 0x830104d to 0x830107a, date = 2023-05-17
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CPU60: No irq handler for vector 27 (IRQ -2147483648)
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microcode: CPU61 updated from revision 0x830107a to 0x830107a, date = 2023-05-17
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This is similar to the issue raised on Linux commit 36e9e1eab777e, where they
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observed i8259 (active) vectors getting delivered to CPUs different than 0.
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On AMD or Hygon platforms adjust the target CPU mask of i8259 interrupt
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descriptors to contain all possible CPUs, so that APs will reserve the vector
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at startup if any legacy IRQ is still delivered through the i8259. Note that
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if the IO-APIC takes over those interrupt descriptors the CPU mask will be
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reset.
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Spurious i8259 interrupt vectors however (IRQ7 and IRQ15) can be injected even
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when all i8259 pins are masked, and hence would need to be handled on all CPUs.
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Continue to reserve PIC vectors on CPU0 only, but do check for such spurious
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interrupts on all CPUs if the vendor is AMD or Hygon. Note that once the
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vectors get used by devices detecting PIC spurious interrupts will no longer be
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possible, however the device driver should be able to cope with spurious
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interrupts. Such PIC spurious interrupts occurring when the vector is in use
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by a local APIC routed source will lead to an extra EOI, which might
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unintentionally clear a different vector from ISR. Note this is already the
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current behavior, so assume it's infrequent enough to not cause real issues.
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Finally, adjust the printed message to display the CPU where the spurious
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interrupt has been received, so it looks like:
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microcode: CPU1 updated from revision 0x830107a to 0x830107a, date = 2023-05-17
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cpu1: spurious 8259A interrupt: IRQ7
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microcode: CPU2 updated from revision 0x830104d to 0x830107a, date = 2023-05-17
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Amends: 3fba06ba9f8b ('x86/IRQ: re-use legacy vector ranges on APs')
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Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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--- a/xen/arch/x86/i8259.c
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+++ b/xen/arch/x86/i8259.c
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@@ -222,7 +222,8 @@ static bool _mask_and_ack_8259A_irq(unsi
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is_real_irq = false;
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/* Report spurious IRQ, once per IRQ line. */
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if (!(spurious_irq_mask & irqmask)) {
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- printk("spurious 8259A interrupt: IRQ%d.\n", irq);
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+ printk("cpu%u: spurious 8259A interrupt: IRQ%u\n",
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+ smp_processor_id(), irq);
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spurious_irq_mask |= irqmask;
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}
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/*
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@@ -349,7 +350,23 @@ void __init init_IRQ(void)
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continue;
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desc->handler = &i8259A_irq_type;
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per_cpu(vector_irq, cpu)[LEGACY_VECTOR(irq)] = irq;
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- cpumask_copy(desc->arch.cpu_mask, cpumask_of(cpu));
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+
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+ /*
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+ * The interrupt affinity logic never targets interrupts to offline
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+ * CPUs, hence it's safe to use cpumask_all here.
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+ *
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+ * Legacy PIC interrupts are only targeted to CPU0, but depending on
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+ * the platform they can be distributed to any online CPU in hardware.
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+ * Note this behavior has only been observed on AMD hardware. In order
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+ * to cope install all active legacy vectors on all CPUs.
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+ *
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+ * IO-APIC will change the destination mask if/when taking ownership of
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+ * the interrupt.
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+ */
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+ cpumask_copy(desc->arch.cpu_mask,
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+ (boot_cpu_data.x86_vendor &
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+ (X86_VENDOR_AMD | X86_VENDOR_HYGON) ? &cpumask_all
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+ : cpumask_of(cpu)));
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desc->arch.vector = LEGACY_VECTOR(irq);
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}
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--- a/xen/arch/x86/irq.c
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+++ b/xen/arch/x86/irq.c
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@@ -1920,7 +1920,16 @@ void do_IRQ(struct cpu_user_regs *regs)
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kind = "";
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if ( !(vector >= FIRST_LEGACY_VECTOR &&
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vector <= LAST_LEGACY_VECTOR &&
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- !smp_processor_id() &&
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+ (!smp_processor_id() ||
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+ /*
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+ * For AMD/Hygon do spurious PIC interrupt
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+ * detection on all CPUs, as it has been observed
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+ * that during unknown circumstances spurious PIC
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+ * interrupts have been delivered to CPUs
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+ * different than the BSP.
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+ */
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+ (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD |
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+ X86_VENDOR_HYGON))) &&
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bogus_8259A_irq(vector - FIRST_LEGACY_VECTOR)) )
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{
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printk("CPU%u: No irq handler for vector %02x (IRQ %d%s)\n",
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