forked from SLFO-pool/xen
61 lines
2.6 KiB
Diff
61 lines
2.6 KiB
Diff
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# Commit 656ae8f1091bcefec9c46ec3ea3ac2118742d4f6
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# Date 2024-04-25 16:37:01 +0200
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# Author Roger Pau Monné <roger.pau@citrix.com>
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# Committer Jan Beulich <jbeulich@suse.com>
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x86/spec: adjust logic that elides lfence
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It's currently too restrictive by just checking whether there's a BHB clearing
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sequence selected. It should instead check whether BHB clearing is used on
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entry from PV or HVM specifically.
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Switch to use opt_bhb_entry_{pv,hvm} instead, and then remove cpu_has_bhb_seq
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since it no longer has any users.
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Reported-by: Jan Beulich <jbeulich@suse.com>
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Fixes: 954c983abcee ('x86/spec-ctrl: Software BHB-clearing sequences')
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Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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--- a/xen/arch/x86/include/asm/cpufeature.h
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+++ b/xen/arch/x86/include/asm/cpufeature.h
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@@ -228,9 +228,6 @@ static inline bool boot_cpu_has(unsigned
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#define cpu_bug_fpu_ptrs boot_cpu_has(X86_BUG_FPU_PTRS)
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#define cpu_bug_null_seg boot_cpu_has(X86_BUG_NULL_SEG)
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-#define cpu_has_bhb_seq (boot_cpu_has(X86_SPEC_BHB_TSX) || \
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- boot_cpu_has(X86_SPEC_BHB_LOOPS))
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-
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enum _cache_type {
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CACHE_TYPE_NULL = 0,
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CACHE_TYPE_DATA = 1,
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--- a/xen/arch/x86/spec_ctrl.c
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+++ b/xen/arch/x86/spec_ctrl.c
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@@ -2328,7 +2328,7 @@ void __init init_speculation_mitigations
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* unconditional WRMSR. If we do have it, or we're not using any
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* prior conditional block, then it's safe to drop the LFENCE.
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*/
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- if ( !cpu_has_bhb_seq &&
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+ if ( !opt_bhb_entry_pv &&
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(boot_cpu_has(X86_FEATURE_SC_MSR_PV) ||
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!boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV)) )
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setup_force_cpu_cap(X86_SPEC_NO_LFENCE_ENTRY_PV);
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@@ -2344,7 +2344,7 @@ void __init init_speculation_mitigations
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* active in the block that is skipped when interrupting guest
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* context, then it's safe to drop the LFENCE.
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*/
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- if ( !cpu_has_bhb_seq &&
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+ if ( !opt_bhb_entry_pv &&
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(boot_cpu_has(X86_FEATURE_SC_MSR_PV) ||
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(!boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) &&
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!boot_cpu_has(X86_FEATURE_SC_RSB_PV))) )
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@@ -2356,7 +2356,7 @@ void __init init_speculation_mitigations
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* A BHB sequence, if used, is the only conditional action, so if we
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* don't have it, we don't need the safety LFENCE.
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*/
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- if ( !cpu_has_bhb_seq )
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+ if ( !opt_bhb_entry_hvm )
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setup_force_cpu_cap(X86_SPEC_NO_LFENCE_ENTRY_VMX);
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}
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