397 lines
14 KiB
C
397 lines
14 KiB
C
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/*
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* STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart
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* by Alistair Francis.
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "chardev/char-fe.h"
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#include "chardev/char-serial.h"
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#include "migration/vmstate.h"
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#include "hw/char/stm32l4x5_usart.h"
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#include "hw/clock.h"
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#include "hw/irq.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/registerfields.h"
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#include "trace.h"
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REG32(CR1, 0x00)
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FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
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FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
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FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
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FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */
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FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */
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FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
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FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
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FIELD(CR1, MME, 13, 1) /* Mute mode enable */
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FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
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FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
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FIELD(CR1, PCE, 10, 1) /* Parity control enable */
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FIELD(CR1, PS, 9, 1) /* Parity selection */
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FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */
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FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */
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FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */
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FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */
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FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */
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FIELD(CR1, TE, 3, 1) /* Transmitter enable */
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FIELD(CR1, RE, 2, 1) /* Receiver enable */
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FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */
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FIELD(CR1, UE, 0, 1) /* USART enable */
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REG32(CR2, 0x04)
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FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */
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FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */
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FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */
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FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */
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FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */
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FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */
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FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */
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FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */
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FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */
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FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */
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FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */
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FIELD(CR2, STOP, 12, 2) /* STOP bits */
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FIELD(CR2, CLKEN, 11, 1) /* Clock enable */
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FIELD(CR2, CPOL, 10, 1) /* Clock polarity */
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FIELD(CR2, CPHA, 9, 1) /* Clock phase */
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FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */
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FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */
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FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */
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FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */
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REG32(CR3, 0x08)
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/* TCBGTIE only on STM32L496xx/4A6xx devices */
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FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */
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FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */
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FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */
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FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */
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FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */
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FIELD(CR3, DEM, 14, 1) /* Driver enable mode */
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FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */
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FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */
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FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */
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FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */
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FIELD(CR3, CTSE, 9, 1) /* CTS enable */
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FIELD(CR3, RTSE, 8, 1) /* RTS enable */
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FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */
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FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */
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FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */
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FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */
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FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */
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FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */
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FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */
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FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */
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REG32(BRR, 0x0C)
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FIELD(BRR, BRR, 0, 16)
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REG32(GTPR, 0x10)
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FIELD(GTPR, GT, 8, 8) /* Guard time value */
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FIELD(GTPR, PSC, 0, 8) /* Prescaler value */
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REG32(RTOR, 0x14)
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FIELD(RTOR, BLEN, 24, 8) /* Block Length */
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FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */
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REG32(RQR, 0x18)
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FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */
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FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */
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FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */
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FIELD(RQR, SBKRQ, 1, 1) /* Send break request */
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FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */
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REG32(ISR, 0x1C)
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/* TCBGT only for STM32L475xx/476xx/486xx devices */
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FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */
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FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */
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FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
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FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
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FIELD(ISR, SBKF, 18, 1) /* Send break flag */
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FIELD(ISR, CMF, 17, 1) /* Character match flag */
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FIELD(ISR, BUSY, 16, 1) /* Busy flag */
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FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */
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FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */
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FIELD(ISR, EOBF, 12, 1) /* End of block flag */
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FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */
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FIELD(ISR, CTS, 10, 1) /* CTS flag */
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FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */
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FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */
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FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */
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FIELD(ISR, TC, 6, 1) /* Transmission complete */
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FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */
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FIELD(ISR, IDLE, 4, 1) /* Idle line detected */
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FIELD(ISR, ORE, 3, 1) /* Overrun error */
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FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */
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FIELD(ISR, FE, 1, 1) /* Framing Error */
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FIELD(ISR, PE, 0, 1) /* Parity Error */
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REG32(ICR, 0x20)
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FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
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FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */
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FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */
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FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
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FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */
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FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */
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/* TCBGTCF only on STM32L496xx/4A6xx devices */
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FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */
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FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */
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FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */
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FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */
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FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */
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FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */
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REG32(RDR, 0x24)
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FIELD(RDR, RDR, 0, 9)
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REG32(TDR, 0x28)
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FIELD(TDR, TDR, 0, 9)
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static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type)
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{
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Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
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s->cr1 = 0x00000000;
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s->cr2 = 0x00000000;
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s->cr3 = 0x00000000;
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s->brr = 0x00000000;
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s->gtpr = 0x00000000;
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s->rtor = 0x00000000;
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s->isr = 0x020000C0;
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s->rdr = 0x00000000;
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s->tdr = 0x00000000;
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}
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static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Stm32l4x5UsartBaseState *s = opaque;
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uint64_t retvalue = 0;
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switch (addr) {
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case A_CR1:
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retvalue = s->cr1;
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break;
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case A_CR2:
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retvalue = s->cr2;
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break;
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case A_CR3:
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retvalue = s->cr3;
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break;
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case A_BRR:
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retvalue = FIELD_EX32(s->brr, BRR, BRR);
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break;
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case A_GTPR:
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retvalue = s->gtpr;
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break;
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case A_RTOR:
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retvalue = s->rtor;
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break;
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case A_RQR:
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/* RQR is a write only register */
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retvalue = 0x00000000;
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break;
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case A_ISR:
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retvalue = s->isr;
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break;
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case A_ICR:
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/* ICR is a clear register */
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retvalue = 0x00000000;
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break;
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case A_RDR:
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retvalue = FIELD_EX32(s->rdr, RDR, RDR);
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/* Reset RXNE flag */
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s->isr &= ~R_ISR_RXNE_MASK;
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break;
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case A_TDR:
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retvalue = FIELD_EX32(s->tdr, TDR, TDR);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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break;
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}
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trace_stm32l4x5_usart_read(addr, retvalue);
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return retvalue;
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}
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static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Stm32l4x5UsartBaseState *s = opaque;
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const uint32_t value = val64;
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trace_stm32l4x5_usart_write(addr, value);
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switch (addr) {
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case A_CR1:
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s->cr1 = value;
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return;
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case A_CR2:
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s->cr2 = value;
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return;
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case A_CR3:
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s->cr3 = value;
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return;
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case A_BRR:
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s->brr = value;
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return;
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case A_GTPR:
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s->gtpr = value;
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return;
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case A_RTOR:
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s->rtor = value;
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return;
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case A_RQR:
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return;
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case A_ISR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: ISR is read only !\n", __func__);
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return;
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case A_ICR:
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/* Clear the status flags */
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s->isr &= ~value;
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return;
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case A_RDR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: RDR is read only !\n", __func__);
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return;
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case A_TDR:
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s->tdr = value;
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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}
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}
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static const MemoryRegionOps stm32l4x5_usart_base_ops = {
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.read = stm32l4x5_usart_base_read,
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.write = stm32l4x5_usart_base_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.max_access_size = 4,
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.min_access_size = 4,
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.unaligned = false
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},
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.impl = {
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.max_access_size = 4,
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.min_access_size = 4,
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.unaligned = false
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},
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};
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static Property stm32l4x5_usart_base_properties[] = {
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DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32l4x5_usart_base_init(Object *obj)
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{
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Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s,
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TYPE_STM32L4X5_USART_BASE, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
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}
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static const VMStateDescription vmstate_stm32l4x5_usart_base = {
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.name = TYPE_STM32L4X5_USART_BASE,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
|
||
|
|
VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState),
|
||
|
|
VMSTATE_END_OF_LIST()
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp)
|
||
|
|
{
|
||
|
|
ERRP_GUARD();
|
||
|
|
Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev);
|
||
|
|
if (!clock_has_source(s->clk)) {
|
||
|
|
error_setg(errp, "USART clock must be wired up by SoC code");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
||
|
|
|
||
|
|
rc->phases.hold = stm32l4x5_usart_base_reset_hold;
|
||
|
|
device_class_set_props(dc, stm32l4x5_usart_base_properties);
|
||
|
|
dc->realize = stm32l4x5_usart_base_realize;
|
||
|
|
dc->vmsd = &vmstate_stm32l4x5_usart_base;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data)
|
||
|
|
{
|
||
|
|
Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
|
||
|
|
|
||
|
|
subc->type = STM32L4x5_USART;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data)
|
||
|
|
{
|
||
|
|
Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
|
||
|
|
|
||
|
|
subc->type = STM32L4x5_UART;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data)
|
||
|
|
{
|
||
|
|
Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
|
||
|
|
|
||
|
|
subc->type = STM32L4x5_LPUART;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo stm32l4x5_usart_types[] = {
|
||
|
|
{
|
||
|
|
.name = TYPE_STM32L4X5_USART_BASE,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(Stm32l4x5UsartBaseState),
|
||
|
|
.instance_init = stm32l4x5_usart_base_init,
|
||
|
|
.class_init = stm32l4x5_usart_base_class_init,
|
||
|
|
.abstract = true,
|
||
|
|
}, {
|
||
|
|
.name = TYPE_STM32L4X5_USART,
|
||
|
|
.parent = TYPE_STM32L4X5_USART_BASE,
|
||
|
|
.class_init = stm32l4x5_usart_class_init,
|
||
|
|
}, {
|
||
|
|
.name = TYPE_STM32L4X5_UART,
|
||
|
|
.parent = TYPE_STM32L4X5_USART_BASE,
|
||
|
|
.class_init = stm32l4x5_uart_class_init,
|
||
|
|
}, {
|
||
|
|
.name = TYPE_STM32L4X5_LPUART,
|
||
|
|
.parent = TYPE_STM32L4X5_USART_BASE,
|
||
|
|
.class_init = stm32l4x5_lpuart_class_init,
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
DEFINE_TYPES(stm32l4x5_usart_types)
|