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										 |  |  | /* HPPA cores and system support chips.  */ | 
					
						
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										 |  |  | /* Be aware: QEMU and seabios-hppa repositories share this file as-is. */ | 
					
						
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										 |  |  | #ifndef HW_HPPA_HPPA_HARDWARE_H
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							|  |  |  | #define HW_HPPA_HPPA_HARDWARE_H
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										 |  |  | #define FIRMWARE_START  0xf0000000
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							|  |  |  | #define FIRMWARE_END    0xf0800000
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							|  |  |  | #define DEVICE_HPA_LEN  0x00100000
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							|  |  |  | #define GSC_HPA         0xffc00000
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							|  |  |  | #define DINO_HPA        0xfff80000
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							|  |  |  | #define DINO_UART_HPA   0xfff83000
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							|  |  |  | #define  DINO_UART_BASE 0xfff83800
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							|  |  |  | #define DINO_SCSI_HPA   0xfff8c000
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							|  |  |  | #define LASI_HPA        0xffd00000
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							|  |  |  | #define LASI_UART_HPA   0xffd05000
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							|  |  |  | #define LASI_SCSI_HPA   0xffd06000
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							|  |  |  | #define LASI_LAN_HPA    0xffd07000
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										 |  |  | #define LASI_RTC_HPA    0xffd09000
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										 |  |  | #define LASI_LPT_HPA    0xffd02000
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							|  |  |  | #define LASI_AUDIO_HPA  0xffd04000
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							|  |  |  | #define LASI_PS2KBD_HPA 0xffd08000
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							|  |  |  | #define LASI_PS2MOU_HPA 0xffd08100
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							|  |  |  | #define LASI_GFX_HPA    0xf8000000
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										 |  |  | #define ARTIST_FB_ADDR  0xf9000000
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										 |  |  | #define CPU_HPA         0xfffb0000
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										 |  |  | #define MEMORY_HPA      0xfffff000
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							|  |  |  | #define PCI_HPA         DINO_HPA        /* PCI bus */
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							|  |  |  | #define IDE_HPA         0xf9000000      /* Boot disc controller */
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										 |  |  | /* offsets to DINO HPA: */ | 
					
						
							|  |  |  | #define DINO_PCI_ADDR           0x064
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							|  |  |  | #define DINO_CONFIG_DATA        0x068
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							|  |  |  | #define DINO_IO_DATA            0x06c
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										 |  |  | #define PORT_PCI_CMD    (PCI_HPA + DINO_PCI_ADDR)
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							|  |  |  | #define PORT_PCI_DATA   (PCI_HPA + DINO_CONFIG_DATA)
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										 |  |  | #define FW_CFG_IO_BASE  0xfffa0000
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										 |  |  | #define PORT_SERIAL1    (LASI_UART_HPA + 0x800)
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							|  |  |  | #define PORT_SERIAL2    (DINO_UART_HPA + 0x800)
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										 |  |  | #define HPPA_MAX_CPUS   16      /* max. number of SMP CPUs */
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										 |  |  | #define CPU_CLOCK_MHZ   250     /* emulate a 250 MHz CPU */
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										 |  |  | #define CPU_HPA_CR_REG  7       /* store CPU HPA in cr7 (SeaBIOS internal) */
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										 |  |  | #define PIM_STORAGE_SIZE 600	/* storage size of pdc_pim_toc_struct (64bit) */
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										 |  |  | #endif
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