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a2cb15b0ddfa05f81a42d7b65dd0c7c50e420c33
qemu/tests/tcg/mips/mips32-dsp/insv.c

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target-mips: Add ASE DSP testcases Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-24 22:17:13 +08:00
#include<stdio.h>
#include<assert.h>
int main()
{
int rt, rs, dsp;
int result;
/* msb = 10, lsb = 5 */
dsp = 0x305;
rt = 0x12345678;
rs = 0x87654321;
target-mips: Fix incorrect code and test for INSV Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-11-26 16:13:21 +01:00
result = 0x12345438;
target-mips: Add ASE DSP testcases Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-24 22:17:13 +08:00
__asm
("wrdsp %2, 0x03\n\t"
"insv %0, %1\n\t"
: "+r"(rt)
: "r"(rs), "r"(dsp)
);
assert(rt == result);
return 0;
}
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