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										 |  |  | /*
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							|  |  |  |  * QEMU Alpha PCI support functions. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Some of this isn't very Alpha specific at all. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * ??? Sparse memory access not implemented. | 
					
						
							|  |  |  |  */ | 
					
						
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										 |  |  | #include "qemu/osdep.h"
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										 |  |  | #include "hw/pci/pci_host.h"
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										 |  |  | #include "alpha_sys.h"
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										 |  |  | #include "qemu/log.h"
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										 |  |  | #include "trace.h"
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										 |  |  | /* Fallback for unassigned PCI I/O operations.  Avoids MCHK.  */ | 
					
						
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							|  |  |  | static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  |     return 0; | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | const MemoryRegionOps alpha_pci_ignore_ops = { | 
					
						
							|  |  |  |     .read = ignore_read, | 
					
						
							|  |  |  |     .write = ignore_write, | 
					
						
							|  |  |  |     .endianness = DEVICE_LITTLE_ENDIAN, | 
					
						
							|  |  |  |     .valid = { | 
					
						
							|  |  |  |         .min_access_size = 1, | 
					
						
							|  |  |  |         .max_access_size = 8, | 
					
						
							|  |  |  |     }, | 
					
						
							|  |  |  |     .impl = { | 
					
						
							|  |  |  |         .min_access_size = 1, | 
					
						
							|  |  |  |         .max_access_size = 8, | 
					
						
							|  |  |  |     }, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | /* PCI config space reads/writes, to byte-word addressable memory.  */ | 
					
						
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										 |  |  | static uint64_t bw_conf1_read(void *opaque, hwaddr addr, | 
					
						
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										 |  |  |                               unsigned size) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  |     PCIBus *b = opaque; | 
					
						
							|  |  |  |     return pci_data_read(b, addr, size); | 
					
						
							|  |  |  | } | 
					
						
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										 |  |  | static void bw_conf1_write(void *opaque, hwaddr addr, | 
					
						
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										 |  |  |                            uint64_t val, unsigned size) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  |     PCIBus *b = opaque; | 
					
						
							|  |  |  |     pci_data_write(b, addr, val, size); | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | const MemoryRegionOps alpha_pci_conf1_ops = { | 
					
						
							|  |  |  |     .read = bw_conf1_read, | 
					
						
							|  |  |  |     .write = bw_conf1_write, | 
					
						
							|  |  |  |     .endianness = DEVICE_LITTLE_ENDIAN, | 
					
						
							|  |  |  |     .impl = { | 
					
						
							|  |  |  |         .min_access_size = 1, | 
					
						
							|  |  |  |         .max_access_size = 4, | 
					
						
							|  |  |  |     }, | 
					
						
							|  |  |  | }; | 
					
						
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							|  |  |  | /* PCI/EISA Interrupt Acknowledge Cycle.  */ | 
					
						
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										 |  |  | static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) | 
					
						
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										 |  |  | { | 
					
						
							|  |  |  |     return pic_read_irq(isa_pic); | 
					
						
							|  |  |  | } | 
					
						
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										 |  |  | static void special_write(void *opaque, hwaddr addr, | 
					
						
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										 |  |  |                           uint64_t val, unsigned size) | 
					
						
							|  |  |  | { | 
					
						
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										 |  |  |     trace_alpha_pci_iack_write(); | 
					
						
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										 |  |  | } | 
					
						
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							|  |  |  | const MemoryRegionOps alpha_pci_iack_ops = { | 
					
						
							|  |  |  |     .read = iack_read, | 
					
						
							|  |  |  |     .write = special_write, | 
					
						
							|  |  |  |     .endianness = DEVICE_LITTLE_ENDIAN, | 
					
						
							|  |  |  |     .valid = { | 
					
						
							|  |  |  |         .min_access_size = 4, | 
					
						
							|  |  |  |         .max_access_size = 4, | 
					
						
							|  |  |  |     }, | 
					
						
							|  |  |  |     .impl = { | 
					
						
							|  |  |  |         .min_access_size = 4, | 
					
						
							|  |  |  |         .max_access_size = 4, | 
					
						
							|  |  |  |     }, | 
					
						
							|  |  |  | }; |