61 lines
2.8 KiB
Plaintext
61 lines
2.8 KiB
Plaintext
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# AArch64 SME allowed instruction decoding
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#
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# Copyright (c) 2022 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# These patterns are taken from Appendix E1.1 of DDI0616 A.a,
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# Arm Architecture Reference Manual Supplement,
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# The Scalable Matrix Extension (SME), for Armv9-A
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{
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[
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OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0]
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OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0]
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OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0]
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OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0]
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OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0]
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OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0]
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OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0]
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]
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FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations
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}
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{
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[
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OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar)
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OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16)
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OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar)
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OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16)
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]
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FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations
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}
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FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store
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FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions
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FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS
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# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions
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# We don't actually need to include these, as the default is OK.
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# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations
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# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers
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# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal)
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# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
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# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
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# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
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