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c8b39c9b5b901b173fbbb0ec3f147e9694ece48c
qemu/tests/tcg/riscv64/test-noc.S

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ArmAsm
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target/riscv: Set pc_succ_insn for !rvc illegal insn Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-12-03 11:57:44 -06:00
#include <asm/unistd.h>
.text
.globl _start
_start:
.option norvc
li a0, 4 /* SIGILL */
la a1, sa
li a2, 0
li a3, 8
li a7, __NR_rt_sigaction
scall
.option rvc
li a0, 1
j exit
.option norvc
pass:
li a0, 0
exit:
li a7, __NR_exit
scall
.data
/* struct kernel_sigaction sa = { .sa_handler = pass }; */
.type sa, @object
.size sa, 32
sa:
.dword pass
.zero 24
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