2016-06-14 15:59:15 +01:00
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/*
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* dpcd.h
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*
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* Copyright (C)2015 : GreenSocs Ltd
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* http://www.greensocs.com/ , email: info@greensocs.com
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*
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* Developed by :
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* Frederic Konrad <fred.konrad@greensocs.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option)any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef DPCD_H
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#define DPCD_H
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typedef struct DPCDState DPCDState;
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#define TYPE_DPCD "dpcd"
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#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
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/* DCPD Revision. */
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#define DPCD_REVISION 0x00
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#define DPCD_REV_1_0 0x10
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#define DPCD_REV_1_1 0x11
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/* DCPD Max Link Rate. */
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#define DPCD_MAX_LINK_RATE 0x01
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#define DPCD_1_62GBPS 0x06
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#define DPCD_2_7GBPS 0x0A
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#define DPCD_5_4GBPS 0x14
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#define DPCD_MAX_LANE_COUNT 0x02
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#define DPCD_ONE_LANE 0x01
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#define DPCD_TWO_LANES 0x02
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#define DPCD_FOUR_LANES 0x04
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/* DCPD Max down spread. */
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#define DPCD_UP_TO_0_5 0x01
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#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
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/* DCPD Downstream port type. */
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#define DPCD_DISPLAY_PORT 0x00
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#define DPCD_ANALOG 0x02
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#define DPCD_DVI_HDMI 0x04
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#define DPCD_OTHER 0x06
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/* DPCD Format conversion. */
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#define DPCD_FORMAT_CONVERSION 0x08
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/* Main link channel coding. */
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#define DPCD_ANSI_8B_10B 0x01
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/* Down stream port count. */
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#define DPCD_OUI_SUPPORTED 0x80
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/* Receiver port capability. */
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#define DPCD_RECEIVE_PORT0_CAP_0 0x08
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#define DPCD_RECEIVE_PORT0_CAP_1 0x09
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#define DPCD_EDID_PRESENT 0x02
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#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
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/* Down stream port capability. */
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#define DPCD_CAP_DISPLAY_PORT 0x000
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#define DPCD_CAP_ANALOG_VGA 0x001
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#define DPCD_CAP_DVI 0x002
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#define DPCD_CAP_HDMI 0x003
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#define DPCD_CAP_OTHER 0x100
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#define DPCD_LANE0_1_STATUS 0x202
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#define DPCD_LANE0_CR_DONE (1 << 0)
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#define DPCD_LANE0_CHANNEL_EQ_DONE (1 << 1)
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#define DPCD_LANE0_SYMBOL_LOCKED (1 << 2)
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#define DPCD_LANE1_CR_DONE (1 << 4)
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#define DPCD_LANE1_CHANNEL_EQ_DONE (1 << 5)
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#define DPCD_LANE1_SYMBOL_LOCKED (1 << 6)
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#define DPCD_LANE2_3_STATUS 0x203
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#define DPCD_LANE2_CR_DONE (1 << 0)
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#define DPCD_LANE2_CHANNEL_EQ_DONE (1 << 1)
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#define DPCD_LANE2_SYMBOL_LOCKED (1 << 2)
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#define DPCD_LANE3_CR_DONE (1 << 4)
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#define DPCD_LANE3_CHANNEL_EQ_DONE (1 << 5)
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#define DPCD_LANE3_SYMBOL_LOCKED (1 << 6)
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#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DPCD_INTERLANE_ALIGN_DONE 0x01
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#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED 0x40
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#define DPCD_LINK_STATUS_UPDATED 0x80
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#define DPCD_SINK_STATUS 0x205
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#define DPCD_RECEIVE_PORT_0_STATUS 0x01
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2016-06-29 15:29:06 +02:00
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#endif /* DPCD_H */
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