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											2015-12-17 13:37:15 +00:00
										 |  |  | /*
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							|  |  |  |  * IMX31 Clock Control Module | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Copyright (C) 2012 NICTA | 
					
						
							|  |  |  |  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This work is licensed under the terms of the GNU GPL, version 2 or later. | 
					
						
							|  |  |  |  * See the COPYING file in the top-level directory. | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | #ifndef IMX31_CCM_H
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							|  |  |  | #define IMX31_CCM_H
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							|  |  |  | #include "hw/misc/imx_ccm.h"
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										 |  |  | #define IMX31_CCM_CCMR_REG  0
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							|  |  |  | #define IMX31_CCM_PDR0_REG  1
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							|  |  |  | #define IMX31_CCM_PDR1_REG  2
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							|  |  |  | #define IMX31_CCM_RCSR_REG  3
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							|  |  |  | #define IMX31_CCM_MPCTL_REG 4
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							|  |  |  | #define IMX31_CCM_UPCTL_REG 5
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							|  |  |  | #define IMX31_CCM_SPCTL_REG 6
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							|  |  |  | #define IMX31_CCM_COSR_REG  7
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							|  |  |  | #define IMX31_CCM_CGR0_REG  8
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							|  |  |  | #define IMX31_CCM_CGR1_REG  9
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							|  |  |  | #define IMX31_CCM_CGR2_REG  10
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							|  |  |  | #define IMX31_CCM_WIMR_REG  11
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							|  |  |  | #define IMX31_CCM_LDC_REG   12
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							|  |  |  | #define IMX31_CCM_DCVR0_REG 13
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							|  |  |  | #define IMX31_CCM_DCVR1_REG 14
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							|  |  |  | #define IMX31_CCM_DCVR2_REG 15
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							|  |  |  | #define IMX31_CCM_DCVR3_REG 16
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							|  |  |  | #define IMX31_CCM_LTR0_REG  17
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							|  |  |  | #define IMX31_CCM_LTR1_REG  18
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							|  |  |  | #define IMX31_CCM_LTR2_REG  19
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							|  |  |  | #define IMX31_CCM_LTR3_REG  20
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							|  |  |  | #define IMX31_CCM_LTBR0_REG 21
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							|  |  |  | #define IMX31_CCM_LTBR1_REG 22
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							|  |  |  | #define IMX31_CCM_PMCR0_REG 23
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							|  |  |  | #define IMX31_CCM_PMCR1_REG 24
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							|  |  |  | #define IMX31_CCM_PDR2_REG  25
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							|  |  |  | #define IMX31_CCM_MAX_REG   26
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										 |  |  | /* CCMR */ | 
					
						
							|  |  |  | #define CCMR_FPME    (1<<0)
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							|  |  |  | #define CCMR_MPE     (1<<3)
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							|  |  |  | #define CCMR_MDS     (1<<7)
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							|  |  |  | #define CCMR_FPMF    (1<<26)
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							|  |  |  | #define CCMR_PRCS    (3<<1)
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							|  |  |  | #define PMCR0_DFSUP1 (1<<31)
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							|  |  |  | /* PDR0 */ | 
					
						
							|  |  |  | #define PDR0_MCU_PODF_SHIFT (0)
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							|  |  |  | #define PDR0_MCU_PODF_MASK (0x7)
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							|  |  |  | #define PDR0_MAX_PODF_SHIFT (3)
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							|  |  |  | #define PDR0_MAX_PODF_MASK (0x7)
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							|  |  |  | #define PDR0_IPG_PODF_SHIFT (6)
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							|  |  |  | #define PDR0_IPG_PODF_MASK (0x3)
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							|  |  |  | #define PDR0_NFC_PODF_SHIFT (8)
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							|  |  |  | #define PDR0_NFC_PODF_MASK (0x7)
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							|  |  |  | #define PDR0_HSP_PODF_SHIFT (11)
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							|  |  |  | #define PDR0_HSP_PODF_MASK (0x7)
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							|  |  |  | #define PDR0_PER_PODF_SHIFT (16)
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							|  |  |  | #define PDR0_PER_PODF_MASK (0x1f)
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							|  |  |  | #define PDR0_CSI_PODF_SHIFT (23)
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							|  |  |  | #define PDR0_CSI_PODF_MASK (0x1ff)
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							|  |  |  | #define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
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							|  |  |  |                               & PDR0_##name##_PODF_MASK) | 
					
						
							|  |  |  | #define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
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							|  |  |  |                              PDR0_##name##_PODF_SHIFT) | 
					
						
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							|  |  |  | #define TYPE_IMX31_CCM "imx31.ccm"
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							|  |  |  | #define IMX31_CCM(obj) OBJECT_CHECK(IMX31CCMState, (obj), TYPE_IMX31_CCM)
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							|  |  |  | typedef struct IMX31CCMState { | 
					
						
							|  |  |  |     /* <private> */ | 
					
						
							|  |  |  |     IMXCCMState parent_obj; | 
					
						
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							|  |  |  |     /* <public> */ | 
					
						
							|  |  |  |     MemoryRegion iomem; | 
					
						
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										 |  |  |     uint32_t reg[IMX31_CCM_MAX_REG]; | 
					
						
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										 |  |  | } IMX31CCMState; | 
					
						
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							|  |  |  | #endif /* IMX31_CCM_H */
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