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target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

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If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.

Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-68-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
2021-12-10 15:56:53 +08:00
committed by Alistair Francis
parent f714361ed7
commit d6c4d3f2a6
1 changed files with 22 additions and 0 deletions
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22
target/riscv/insn_trans/trans_rvv.c.inc
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@@ -2374,6 +2374,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
int rm)
{
if (checkfn(s, a)) {
if (rm != RISCV_FRM_DYN) {
gen_set_rm(s, RISCV_FRM_DYN);
}
uint32_t data = 0;
TCGLabel *over = gen_new_label();
gen_set_rm(s, rm);
@@ -2459,6 +2463,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
gen_set_rm(s, RISCV_FRM_DYN);
TCGv_i64 t1;
if (s->vl_eq_vlmax) {
@@ -2540,6 +2546,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_widen_check(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
\
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
@@ -2627,6 +2637,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_narrow_check(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
\
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
@@ -2668,6 +2682,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opxfv_narrow_check(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
\
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_##HELPER##_b, \
@@ -3138,6 +3156,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
unsigned int ofs = (8 << s->sew);
unsigned int len = 64 - ofs;
TCGv_i64 t_nan;
@@ -3162,6 +3182,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
/* The instructions ignore LMUL and vector register group. */
TCGv_i64 t1;
TCGLabel *over = gen_new_label();