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target/i386: reimplement 0x0f 0x28-0x2f, add AVX

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Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit.  There is also a mistake in the
manual with respect to the size of the memory operand of CVTPS2PI
and CVTTPS2PI, reported by Ricky Zhou.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
2022-09-06 18:44:02 +02:00
parent 7170a17ec3
commit f8d19eec0d
3 changed files with 185 additions and 0 deletions
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56
target/i386/tcg/decode-new.c.inc
View File

@@ -672,6 +672,53 @@ static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2A[4] = {
X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
};
*entry = *decode_by_prefix(s, opcodes_0F2A);
}
static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2B[4] = {
X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */
X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */
X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */
X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */
};
*entry = *decode_by_prefix(s, opcodes_0F2B);
}
static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2C[4] = {
/* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */
X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q),
X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq),
X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3),
X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3),
};
*entry = *decode_by_prefix(s, opcodes_0F2C);
}
static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2D[4] = {
/* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */
X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q),
X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq),
X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3),
X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3),
};
*entry = *decode_by_prefix(s, opcodes_0F2D);
}
static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
@@ -746,6 +793,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x77] = X86_OP_GROUP0(0F77),
[0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
[0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
[0x2A] = X86_OP_GROUP0(0F2A),
[0x2B] = X86_OP_GROUP0(0F2B),
[0x2C] = X86_OP_GROUP0(0F2C),
[0x2D] = X86_OP_GROUP0(0F2D),
[0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_66),
[0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_66),
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),

128
target/i386/tcg/emit.c.inc
View File

@@ -1038,6 +1038,36 @@ static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_constant_i32(8 << ot));
}
static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_helper_enter_mmx(cpu_env);
if (s->prefix & PREFIX_DATA) {
gen_helper_cvtpi2pd(cpu_env, OP_PTR0, OP_PTR2);
} else {
gen_helper_cvtpi2ps(cpu_env, OP_PTR0, OP_PTR2);
}
}
static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_helper_enter_mmx(cpu_env);
if (s->prefix & PREFIX_DATA) {
gen_helper_cvtpd2pi(cpu_env, OP_PTR0, OP_PTR2);
} else {
gen_helper_cvtps2pi(cpu_env, OP_PTR0, OP_PTR2);
}
}
static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_helper_enter_mmx(cpu_env);
if (s->prefix & PREFIX_DATA) {
gen_helper_cvttpd2pi(cpu_env, OP_PTR0, OP_PTR2);
} else {
gen_helper_cvttps2pi(cpu_env, OP_PTR0, OP_PTR2);
}
}
static void gen_EMMS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_helper_emms(cpu_env);
@@ -1724,6 +1754,14 @@ static void gen_VCMP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_helper_cmp_funcs[index][b](cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
SSEFunc_0_epp fn;
fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss;
fn(cpu_env, OP_PTR1, OP_PTR2);
set_cc_op(s, CC_OP_EFLAGS);
}
static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_unary_fp_sse(s, env, decode,
@@ -1732,6 +1770,88 @@ static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
gen_helper_cvtsd2ss, gen_helper_cvtss2sd);
}
static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int vec_len = vector_len(s, decode);
TCGv_i32 in;
tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
#ifdef TARGET_X86_64
MemOp ot = decode->op[2].ot;
if (ot == MO_64) {
if (s->prefix & PREFIX_REPNZ) {
gen_helper_cvtsq2sd(cpu_env, OP_PTR0, s->T1);
} else {
gen_helper_cvtsq2ss(cpu_env, OP_PTR0, s->T1);
}
return;
}
in = s->tmp2_i32;
tcg_gen_trunc_tl_i32(in, s->T1);
#else
in = s->T1;
#endif
if (s->prefix & PREFIX_REPNZ) {
gen_helper_cvtsi2sd(cpu_env, OP_PTR0, in);
} else {
gen_helper_cvtsi2ss(cpu_env, OP_PTR0, in);
}
}
static inline void gen_VCVTtSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
SSEFunc_i_ep ss2si, SSEFunc_l_ep ss2sq,
SSEFunc_i_ep sd2si, SSEFunc_l_ep sd2sq)
{
TCGv_i32 out;
#ifdef TARGET_X86_64
MemOp ot = decode->op[0].ot;
if (ot == MO_64) {
if (s->prefix & PREFIX_REPNZ) {
sd2sq(s->T0, cpu_env, OP_PTR2);
} else {
ss2sq(s->T0, cpu_env, OP_PTR2);
}
return;
}
out = s->tmp2_i32;
#else
out = s->T0;
#endif
if (s->prefix & PREFIX_REPNZ) {
sd2si(out, cpu_env, OP_PTR2);
} else {
ss2si(out, cpu_env, OP_PTR2);
}
#ifdef TARGET_X86_64
tcg_gen_extu_i32_tl(s->T0, out);
#endif
}
#ifndef TARGET_X86_64
#define gen_helper_cvtss2sq NULL
#define gen_helper_cvtsd2sq NULL
#define gen_helper_cvttss2sq NULL
#define gen_helper_cvttsd2sq NULL
#endif
static void gen_VCVTSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_VCVTtSx2SI(s, env, decode,
gen_helper_cvtss2si, gen_helper_cvtss2sq,
gen_helper_cvtsd2si, gen_helper_cvtsd2sq);
}
static void gen_VCVTTSx2SI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_VCVTtSx2SI(s, env, decode,
gen_helper_cvttss2si, gen_helper_cvttss2sq,
gen_helper_cvttsd2si, gen_helper_cvttsd2sq);
}
static void gen_VEXTRACTx128(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int mask = decode->immediate & 1;
@@ -1987,6 +2107,14 @@ static void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
fn(OP_PTR0, OP_PTR1, OP_PTR2, imm);
}
static void gen_VUCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
SSEFunc_0_epp fn;
fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss;
fn(cpu_env, OP_PTR1, OP_PTR2);
set_cc_op(s, CC_OP_EFLAGS);
}
static void gen_VZEROALL(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_ptr ptr = tcg_temp_new_ptr();

1
target/i386/tcg/translate.c
View File

@@ -4784,6 +4784,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (use_new &&
(b == 0x138 || b == 0x13a ||
(b >= 0x110 && b <= 0x117) ||
(b >= 0x128 && b <= 0x12f) ||
(b >= 0x150 && b <= 0x17f) ||
b == 0x1c2 || (b >= 0x1c4 && b <= 0x1c6) ||
(b >= 0x1d0 && b <= 0x1ff))) {