Frank Chang
75804f7131
target/riscv: add "set round to odd" rounding mode helper function
...
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-64-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
Frank Chang
986c895de1
target/riscv: introduce floating-point rounding mode enum
...
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20211210075704.23951-61-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:53:31 +10:00
Frank Chang
5c4eb8fb56
target/riscv: rvv-1.0: floating-point scalar move instructions
...
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-39-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Frank Chang
f9298de514
target/riscv: rvv-1.0: remove MLEN calculations
...
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20211210075704.23951-13-frank.chang@sifive.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Kito Cheng
00c1899f12
target/riscv: zfh: half-precision computational
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Yifei Jiang
f7697f0e62
target/riscv: Add basic vmstate description of CPU
...
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com >
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-11-03 07:17:23 -08:00
Richard Henderson
00e925c560
target/riscv: Check nanboxed inputs to fp helpers
...
If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-21 22:37:55 -07:00
Richard Henderson
9921e3d330
target/riscv: Generate nanboxed results from fp helpers
...
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-08-21 22:37:55 -07:00
LIU Zhiwei
9fc08be626
target/riscv: integer scalar move instruction
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
LIU Zhiwei
121ddbb36f
target/riscv: vector floating-point classify instructions
...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-41-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
LIU Zhiwei
268fcca66b
target/riscv: add vector amo operations
...
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:33 -07:00
LIU Zhiwei
751538d5da
target/riscv: add vector stride load and store instructions
...
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
LIU Zhiwei
f476f17740
target/riscv: add an internals.h header
...
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20200701152549.1218-6-zhiwei_liu@c-sky.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2020-07-02 09:19:32 -07:00
