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249 Commits

Author SHA1 Message Date
Richard Henderson
d2a0c3a7f7 target/sparc: Add gen_trap_if_nofpu_fpexception 
Model fp_exception state, in which only fp stores are allowed
until such time as the FQ has been flushed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>
 2024-09-11 19:54:55 -07:00
Richard Henderson
29b99802aa target/sparc: Implement STDFQ 
Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>
 2024-09-11 19:54:51 -07:00
Richard Henderson
5a165e2615 target/sparc: Add FSR_QNE to tb_flags 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>
 2024-09-11 19:54:47 -07:00
Richard Henderson
12d36294a2 target/sparc: Restrict STQF to sparcv9 
Prior to sparcv9, the same encoding was STDFQ.

Cc: qemu-stable@nongnu.org
Fixes: 06c060d9e5 ("target/sparc: Move simple fp load/store to decodetree")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2024-08-20 00:49:14 +02:00
Richard Henderson
eeb3f592cb target/sparc: Implement monitor ASIs 
Ignore the "monitor" portion and treat them the same
as their base ASIs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:11:17 -07:00
Richard Henderson
6fbc032cbc target/sparc: Implement MWAIT 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:10:02 -07:00
Richard Henderson
56f2ef9c79 target/sparc: Implement SUBXC, SUBXCcc 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:10:02 -07:00
Richard Henderson
db11dfea83 target/sparc: Implement FPMIN, FPMAX 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:10:02 -07:00
Richard Henderson
b3c934dd34 target/sparc: Implement VIS4 comparisons 
VIS4 completes the set, adding missing signed 8-bit ops
and missing unsigned 16 and 32-bit ops.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:09:36 -07:00
Richard Henderson
b99c1bbddd target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:09:36 -07:00
Richard Henderson
b2b4849336 target/sparc: Implement FALIGNDATAi 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:54 -07:00
Richard Henderson
90b1433da8 target/sparc: Add feature bit for VIS4 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:39 -07:00
Richard Henderson
68a414e99d target/sparc: Implement IMA extension 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:39 -07:00
Richard Henderson
029b0283df target/sparc: Implement XMULX 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:39 -07:00
Richard Henderson
680af1b4a5 target/sparc: Implement UMULXHI 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:39 -07:00
Richard Henderson
7d5ebd8ffe target/sparc: Implement PDISTN 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:39 -07:00
Richard Henderson
09b157e628 target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:16 -07:00
Richard Henderson
875ce3929a target/sparc: Implement LZCNT 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:08:16 -07:00
Richard Henderson
298c52f784 target/sparc: Implement LDXEFSR 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:07:34 -07:00
Richard Henderson
fbc5c8d4e8 target/sparc: Implement FSLL, FSRL, FSRA, FSLAS 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:07:34 -07:00
Richard Henderson
669e077437 target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:06:32 -07:00
Richard Henderson
0d1d3aaf64 target/sparc: Implement FPADDS, FPSUBS 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:53 -07:00
Richard Henderson
bc3f14a9ed target/sparc: Implement FPADD64, FPSUB64 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:53 -07:00
Richard Henderson
d6ff1ccb45 target/sparc: Implement FMEAN16 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:53 -07:00
Richard Henderson
1d3ed3d728 target/sparc: Implement FLCMP 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:53 -07:00
Richard Henderson
3d50b7287e target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:53 -07:00
Richard Henderson
7837185e40 target/sparc: Implement FCHKSM16 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:41 -07:00
Richard Henderson
c973b4e8df target/sparc: Implement CMASK instructions 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:11 -07:00
Richard Henderson
015fc6fcdb target/sparc: Implement ADDXC, ADDXCcc 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
3335a04806 target/sparc: Add feature bits for VIS 3 
The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus.  For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
4fd71d19ac target/sparc: Implement FMAf extension 
Rearrange PDIST so that do_dddd is general purpose and may
be re-used for FMADDd etc.  Add pickNaN and pickNaNMulAdd.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
28c131a34d target/sparc: Use gvec for VIS1 parallel add/sub 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
1210a0367d target/sparc: Remove cpu_fpr[] 
Use explicit loads and stores to env instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
52f46d4627 target/sparc: Remove gen_dest_fpr_D 
Replace with tcg_temp_new_i64.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
0bba7572d4 target/sparc: Perform DFPREG/QFPREG in decodetree 
Form the proper register decoding from the start.

Because we're removing the translation from the inner-most
gen_load_fpr_* and gen_store_fpr_* routines, this must be
done for all insns at once.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
04d5bf3041 target/sparc: Fix do_dc 
Apply DFPREG to compute the register number.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
43db583802 target/sparc: Rewrite gen_edge 
Drop the tables and compute the left and right edges directly.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-06-05 09:05:10 -07:00
Richard Henderson
962a145cdc accel/tcg: Provide default implementation of disas_log 
Almost all of the disas_log implementations are identical.
Unify them within translator_loop.

Drop extra Priv/Virt logging from target/riscv.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-05-15 08:55:18 +02:00
Richard Henderson
d3ef26afde target/sparc: Fix FPMERGE 
This instruction has f32 inputs, which changes the decode
of the register numbers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-7-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
 2024-05-05 21:02:48 +01:00
Richard Henderson
be8998e046 target/sparc: Fix FMULD8*X16 
Not only do these instructions have f32 inputs, they also do not
perform rounding.  Since these are relatively simple, implement
them properly inline.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240502165528.244004-6-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
 2024-05-05 21:02:48 +01:00
Richard Henderson
a859602c74 target/sparc: Fix FMUL8x16A{U,L} 
These instructions have f32 inputs, which changes the decode
of the register numbers.  While we're fixing things, use a
common helper for both insns, extracting the 16-bit scalar
in tcg beforehand.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-5-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
 2024-05-05 21:02:48 +01:00
Richard Henderson
9157dccc7e target/sparc: Fix FMUL8x16 
This instruction has f32 as source1, which alters the
decoding of the register number, which means we've been
passing the wrong data for odd register numbers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-4-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
 2024-05-05 21:02:48 +01:00
Richard Henderson
7b616f36de target/sparc: Fix FEXPAND 
This is a 2-operand instruction, not 3-operand.
Worse, we took the source from the wrong operand.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-3-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
 2024-05-05 21:02:48 +01:00
Richard Henderson
2786a3f8d3 target/sparc: Use GET_ASI_CODE for ASI_KERNELTXT and ASI_USERTXT 
Reads are done with execute access.  It is not clear whether writes
are legal at all -- for now, leave helper_st_asi unchanged, so that
we continue to raise an mmu fault.

This generalizes the exiting code for ASI_KERNELTXT to be usable for
ASI_USERTXT as well, by passing down the MemOpIdx to use.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2281
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2059
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1609
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1166
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: M Bazz <bazz@bazz1.com>
 2024-04-12 14:48:01 -07:00
Philippe Mathieu-Daudé
7797676965 target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro 
Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240129164514.73104-27-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
 2024-03-12 12:04:25 +01:00
Clément Chigot
c92948f22b target/sparc: implement asr17 feature for smp 
This allows the guest program to know its cpu id.

Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-6-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2024-02-15 16:58:46 +01:00
Richard Henderson
50280618d9 target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2024-02-03 23:43:50 +00:00
Richard Henderson
d8c5b92f3f target/sparc: Split fcc out of env->fsr 
Represent each fcc field separately from the rest of fsr.
This vastly simplifies floating-point comparisons.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-22-richard.henderson@linaro.org>
 2024-02-03 16:46:10 +10:00
Richard Henderson
c9fa8e586b target/sparc: Remove cpu_fsr 
Drop this field as a tcg global, loading it explicitly in the
few places required.  This means that all FPop helpers may
once again be TCG_CALL_NO_WG.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-21-richard.henderson@linaro.org>
 2024-02-03 16:46:10 +10:00
Richard Henderson
3590f01ed2 target/sparc: Split cexc and ftt from env->fsr 
These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>
 2024-02-03 16:46:10 +10:00