Bastian Koppelmann
8dc9e8a8b0
target/riscv: Rename trans_arith to gen_arith
...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
34446e8458
target/riscv: Remove shift and slt insn manual decoding
...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
f2ab172867
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
...
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
7a50d3e2ae
target/riscv: Move gen_arith_imm() decoding into trans_* functions
...
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
bce8a342a1
target/riscv: Remove manual decoding from gen_store()
...
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
98898b20e9
target/riscv: Remove manual decoding from gen_load()
...
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
090cc2c898
target/riscv: Remove manual decoding from gen_branch()
...
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
9e92c57d83
target/riscv: Remove gen_jalr()
...
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:40:50 +01:00
Bastian Koppelmann
771fbe156a
target/riscv: Convert RVXI csr insns to decodetree
...
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
Bastian Koppelmann
0c865e856a
target/riscv: Convert RVXI fence insns to decodetree
...
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
Bastian Koppelmann
b73a987b09
target/riscv: Convert RVXI arithmetic insns to decodetree
...
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
Bastian Koppelmann
7e45a682ed
target/riscv: Convert RV64I load/store insns to decodetree
...
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
Bastian Koppelmann
c1000d4e1b
target/riscv: Convert RV32I load/store insns to decodetree
...
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
Bastian Koppelmann
3cca75a6fe
target/riscv: Convert RVXI branch insns to decodetree
...
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Reviewed-by: Palmer Dabbelt <palmer@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
Bastian Koppelmann
2a53cff418
target/riscv: Activate decodetree and implemnt LUI & AUIPC
...
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de >
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de >
2019-03-13 10:34:06 +01:00
