Ard Biesheuvel
7d496bb502
target/riscv: Use accelerated helper for AES64KS1I
...
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.
Cc: Richard Henderson <richard.henderson@linaro.org >
Cc: Philippe Mathieu-Daudé <philmd@linaro.org >
Cc: Palmer Dabbelt <palmer@dabbelt.com >
Cc: Alistair Francis <alistair.francis@wdc.com >
Signed-off-by: Ard Biesheuvel <ardb@kernel.org >
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-ID: <20230831154118.138727-1-ardb@kernel.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-09-11 11:45:55 +10:00
Ard Biesheuvel
9ea17007c4
target/riscv: Use existing lookup tables for MixColumns
...
The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.
Given that we already carry those tables in QEMU, we can just grab the
right value in the implementation of the RISC-V AES32 instructions. Note
that the tables in question are permuted according to the respective
Sbox, so we can omit the Sbox lookup as well in this case.
Cc: Richard Henderson <richard.henderson@linaro.org >
Cc: Philippe Mathieu-Daudé <philmd@linaro.org >
Cc: Zewen Ye <lustrew@foxmail.com >
Cc: Weiwei Li <liweiwei@iscas.ac.cn >
Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Signed-off-by: Ard Biesheuvel <ardb@kernel.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-ID: <20230731084043.1791984-1-ardb@kernel.org >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-09-11 11:45:54 +10:00
Richard Henderson
4ad6f9bfa0
target/riscv: Use aesdec_ISB_ISR_IMC_AK
...
This implements the AES64DSM instruction. This was the last use
of aes64_operation and its support macros, so remove them all.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-07-09 13:47:17 +01:00
Richard Henderson
274f33765a
target/riscv: Use aesenc_SB_SR_MC_AK
...
This implements the AES64ESM instruction.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-07-09 13:47:17 +01:00
Richard Henderson
607a5f9d62
target/riscv: Use aesdec_IMC
...
This implements the AES64IM instruction.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-07-09 13:47:11 +01:00
Richard Henderson
7a70583a41
target/riscv: Use aesdec_ISB_ISR_AK
...
This implements the AES64DS instruction.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-07-09 13:47:11 +01:00
Richard Henderson
cad26538e8
target/riscv: Use aesenc_SB_SR_AK
...
This implements the AES64ES instruction.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-07-09 13:47:11 +01:00
Weiwei Li
0976083d1b
target/riscv: rvk: add support for zksed/zksh extension
...
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
Weiwei Li
9e33e1753b
target/riscv: rvk: add support for zkne/zknd extension in RV64
...
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com >
Co-authored-by: Zewen Ye <lustrew@foxmail.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
Weiwei Li
68d19b58f4
target/riscv: rvk: add support for zknd/zkne extension in RV32
...
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com >
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-04-29 10:47:45 +10:00
