Richard Henderson
ad75a51e84
tcg: Rename cpu_env to tcg_env
...
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-10-03 08:01:02 -07:00
Michael Tokarev
42fe74998c
riscv: spelling fixes
...
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
2023-09-08 13:08:52 +03:00
Weiwei Li
5d1270caac
target/riscv: Add support for Zfbfmin extension
...
Add trans_* and helper function for Zfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20230615063302.102409-3-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-07-10 22:29:15 +10:00
Richard Henderson
2f668fabbc
target/riscv: Avoid tcg_const_*
...
All uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-03-05 13:46:13 -08:00
Richard Henderson
f43442961e
target/riscv: Drop tcg_temp_free
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Translators are no longer required to free tcg temporaries.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-03-05 13:44:08 -08:00
Richard Henderson
574f31161e
target/riscv: Drop temp_new
...
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Signed-off-by: Richard Henderson <richard.henderson@linaro.org >
2023-03-05 13:44:08 -08:00
Weiwei Li
94bdf6ee10
target/riscv: Simplify the check for Zfhmin and Zhinxmin
...
We needn't check Zfh and Zhinx in these instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com >
Message-ID: <20230215020539.4788-4-liweiwei@iscas.ac.cn >
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com >
2023-03-01 14:57:32 -08:00
Anup Patel
f008a2d218
target/riscv: Ensure opcode is saved for all relevant instructions
...
We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a guest page
fault because generating transformed instruction upon guest page fault
expects opcode to be available. Without this, hypervisor will see
transformed instruction as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08apatel@ventanamicro.com >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2023-02-07 08:19:23 +10:00
Weiwei Li
a2464a4cec
target/riscv: add support for zhinx/zhinxmin
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- update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
- update half float point register read/write
- disable nanbox_h check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn >
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn >
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-03-03 13:14:50 +10:00
Philipp Tomsich
79bf3b51ac
target/riscv: access configuration through cfg_ptr in DisasContext
...
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Suggested-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu >
[ Changes by AF:
- Fixup checkpatch failures
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2022-02-16 12:24:18 +10:00
Frank Chang
2d258b428b
target/riscv: zfh: implement zfhmin extension
...
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h, fcvt.h.d
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Kito Cheng
6bc6fc96d1
target/riscv: zfh: half-precision floating-point classify
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Kito Cheng
11f9c450a6
target/riscv: zfh: half-precision floating-point compare
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Kito Cheng
7b03c8e5b5
target/riscv: zfh: half-precision convert and move
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Acked-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Kito Cheng
00c1899f12
target/riscv: zfh: half-precision computational
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Reviewed-by: Alistair Francis <alistair.francis@wdc.com >
Message-id: 20211210074329.5775-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
Kito Cheng
915f77b211
target/riscv: zfh: half-precision load and store
...
Signed-off-by: Kito Cheng <kito.cheng@sifive.com >
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com >
Signed-off-by: Frank Chang <frank.chang@sifive.com >
Reviewed-by: Richard Henderson <richard.henderson@linaro.org >
Message-id: 20211210074329.5775-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com >
2021-12-20 14:51:36 +10:00
