Christian Borntraeger 2a7569e751 s390/sclp: improve special wait psw logic ...

There is a special quiesce PSW that we check for "shutdown". Otherwise disabled
wait is detected as "crashed". Architecturally we must only check PSW bits
116-127. Fix this.

Cc: qemu-stable@nongnu.org
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Message-Id: <1582204582-22995-1-git-send-email-borntraeger@de.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Acked-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
(cherry picked from commit 8b51c0961c)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

2020-06-02 10:40:21 -05:00

..

alpha

target/alpha: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

arm

target/arm: Set ISSIs16Bit in make_issinfo

2020-05-11 18:08:09 -05:00

cris

cputlb: ensure _cmmu helper functions follow the naming standard

2019-10-28 15:12:38 +00:00

hppa

target/hppa: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

i386

i386: Resolve CPU models to v1 by default

2020-05-11 14:43:25 -05:00

lm32

Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging

2019-08-22 10:31:21 +01:00

m68k

target/m68k: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

microblaze

target/microblaze: Plug temp leak around eval_cond_jmp()

2019-11-12 16:35:26 +01:00

mips

target/mips: Refactor handling of vector compare 'less than' (signed) instructions

2019-10-25 18:37:01 +02:00

moxie

hw/core: Move cpu.c, cpu.h from qom/ to hw/core/

2019-08-21 13:24:01 +02:00

nios2

Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging

2019-08-22 10:31:21 +01:00

openrisc

target/openrisc: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

ppc

spapr/kvm: Set default cpu model for all machine classes

2019-11-18 11:50:39 +01:00

riscv

target/riscv: Remove atomic accesses to MIP CSR

2019-11-14 09:53:28 -08:00

s390x

s390/sclp: improve special wait psw logic

2020-06-02 10:40:21 -05:00

sh4

target/sh4: fetch code with translator_ld

2019-10-28 15:12:38 +00:00

sparc

target/sparc: Define an enumeration for accessing env->regwptr

2019-11-06 13:35:25 +01:00

tilegx

tcg: TCGMemOp is now accelerator independent MemOp

2019-09-03 08:30:38 -07:00

tricore

tcg: TCGMemOp is now accelerator independent MemOp

2019-09-03 08:30:38 -07:00

unicore32

Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging

2019-08-22 10:31:21 +01:00

xtensa

target/xtensa: fetch code with translator_ld

2019-10-28 15:12:38 +00:00