2df59b73e0
Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But,
as per the principles of operation, bit 5 is ignored in MSCH and bits 0,
1, 6 and 7 need to be zero.
As both PMCW_FLAGS_MASK_INVALID and ioinst_schib_valid() are only used
by ioinst_handle_msch(), adjust the mask accordingly.
Fixes: db1c8f53bf ("s390: Channel I/O basic definitions.")
Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.ibm.com>
Reviewed-by: Halil Pasic <pasic@linux.ibm.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20211216131657.1057978-1-nrb@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
259 lines
7.4 KiB
C
259 lines
7.4 KiB
C
/*
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* S/390 channel I/O instructions
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*
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* Copyright 2012 IBM Corp.
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* Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef S390X_IOINST_H
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#define S390X_IOINST_H
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/*
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* Channel I/O related definitions, as defined in the Principles
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* Of Operation (and taken from the Linux implementation).
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*/
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/* subchannel status word (command mode only) */
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typedef struct SCSW {
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uint16_t flags;
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uint16_t ctrl;
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uint32_t cpa;
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uint8_t dstat;
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uint8_t cstat;
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uint16_t count;
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} SCSW;
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QEMU_BUILD_BUG_MSG(sizeof(SCSW) != 12, "size of SCSW is wrong");
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#define SCSW_FLAGS_MASK_KEY 0xf000
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#define SCSW_FLAGS_MASK_SCTL 0x0800
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#define SCSW_FLAGS_MASK_ESWF 0x0400
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#define SCSW_FLAGS_MASK_CC 0x0300
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#define SCSW_FLAGS_MASK_FMT 0x0080
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#define SCSW_FLAGS_MASK_PFCH 0x0040
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#define SCSW_FLAGS_MASK_ISIC 0x0020
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#define SCSW_FLAGS_MASK_ALCC 0x0010
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#define SCSW_FLAGS_MASK_SSI 0x0008
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#define SCSW_FLAGS_MASK_ZCC 0x0004
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#define SCSW_FLAGS_MASK_ECTL 0x0002
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#define SCSW_FLAGS_MASK_PNO 0x0001
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#define SCSW_CTRL_MASK_FCTL 0x7000
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#define SCSW_CTRL_MASK_ACTL 0x0fe0
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#define SCSW_CTRL_MASK_STCTL 0x001f
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#define SCSW_FCTL_CLEAR_FUNC 0x1000
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#define SCSW_FCTL_HALT_FUNC 0x2000
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#define SCSW_FCTL_START_FUNC 0x4000
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#define SCSW_ACTL_SUSP 0x0020
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#define SCSW_ACTL_DEVICE_ACTIVE 0x0040
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#define SCSW_ACTL_SUBCH_ACTIVE 0x0080
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#define SCSW_ACTL_CLEAR_PEND 0x0100
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#define SCSW_ACTL_HALT_PEND 0x0200
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#define SCSW_ACTL_START_PEND 0x0400
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#define SCSW_ACTL_RESUME_PEND 0x0800
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#define SCSW_STCTL_STATUS_PEND 0x0001
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#define SCSW_STCTL_SECONDARY 0x0002
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#define SCSW_STCTL_PRIMARY 0x0004
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#define SCSW_STCTL_INTERMEDIATE 0x0008
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#define SCSW_STCTL_ALERT 0x0010
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#define SCSW_DSTAT_ATTENTION 0x80
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#define SCSW_DSTAT_STAT_MOD 0x40
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#define SCSW_DSTAT_CU_END 0x20
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#define SCSW_DSTAT_BUSY 0x10
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#define SCSW_DSTAT_CHANNEL_END 0x08
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#define SCSW_DSTAT_DEVICE_END 0x04
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#define SCSW_DSTAT_UNIT_CHECK 0x02
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#define SCSW_DSTAT_UNIT_EXCEP 0x01
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#define SCSW_CSTAT_PCI 0x80
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#define SCSW_CSTAT_INCORR_LEN 0x40
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#define SCSW_CSTAT_PROG_CHECK 0x20
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#define SCSW_CSTAT_PROT_CHECK 0x10
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#define SCSW_CSTAT_DATA_CHECK 0x08
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#define SCSW_CSTAT_CHN_CTRL_CHK 0x04
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#define SCSW_CSTAT_INTF_CTRL_CHK 0x02
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#define SCSW_CSTAT_CHAIN_CHECK 0x01
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/* path management control word */
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typedef struct PMCW {
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uint32_t intparm;
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uint16_t flags;
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uint16_t devno;
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uint8_t lpm;
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uint8_t pnom;
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uint8_t lpum;
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uint8_t pim;
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uint16_t mbi;
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uint8_t pom;
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uint8_t pam;
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uint8_t chpid[8];
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uint32_t chars;
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} PMCW;
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QEMU_BUILD_BUG_MSG(sizeof(PMCW) != 28, "size of PMCW is wrong");
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#define PMCW_FLAGS_MASK_QF 0x8000
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#define PMCW_FLAGS_MASK_W 0x4000
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#define PMCW_FLAGS_MASK_ISC 0x3800
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#define PMCW_FLAGS_MASK_ENA 0x0080
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#define PMCW_FLAGS_MASK_LM 0x0060
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#define PMCW_FLAGS_MASK_MME 0x0018
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#define PMCW_FLAGS_MASK_MP 0x0004
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#define PMCW_FLAGS_MASK_TF 0x0002
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#define PMCW_FLAGS_MASK_DNV 0x0001
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#define PMCW_FLAGS_MASK_INVALID 0xc300
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#define PMCW_CHARS_MASK_ST 0x00e00000
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#define PMCW_CHARS_MASK_MBFC 0x00000004
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#define PMCW_CHARS_MASK_XMWME 0x00000002
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#define PMCW_CHARS_MASK_CSENSE 0x00000001
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#define PMCW_CHARS_MASK_INVALID 0xff1ffff8
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/* subchannel information block */
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typedef struct SCHIB {
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PMCW pmcw;
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SCSW scsw;
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uint64_t mba;
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uint8_t mda[4];
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} QEMU_PACKED SCHIB;
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/* format-0 extended-status word */
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typedef struct ESW {
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uint32_t word0; /* subchannel logout for format 0 */
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uint32_t erw;
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uint64_t word2; /* failing-storage address for format 0 */
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uint32_t word4; /* secondary-CCW address for format 0 */
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} QEMU_PACKED ESW;
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#define ESW_ERW_SENSE 0x01000000
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/* interruption response block */
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typedef struct IRB {
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SCSW scsw;
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ESW esw;
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uint32_t ecw[8];
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uint32_t emw[8];
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} IRB;
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QEMU_BUILD_BUG_MSG(sizeof(IRB) != 96, "size of IRB is wrong");
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/* operation request block */
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typedef struct ORB {
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uint32_t intparm;
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uint16_t ctrl0;
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uint8_t lpm;
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uint8_t ctrl1;
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uint32_t cpa;
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} ORB;
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QEMU_BUILD_BUG_MSG(sizeof(ORB) != 12, "size of ORB is wrong");
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#define ORB_CTRL0_MASK_KEY 0xf000
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#define ORB_CTRL0_MASK_SPND 0x0800
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#define ORB_CTRL0_MASK_STR 0x0400
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#define ORB_CTRL0_MASK_MOD 0x0200
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#define ORB_CTRL0_MASK_SYNC 0x0100
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#define ORB_CTRL0_MASK_FMT 0x0080
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#define ORB_CTRL0_MASK_PFCH 0x0040
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#define ORB_CTRL0_MASK_ISIC 0x0020
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#define ORB_CTRL0_MASK_ALCC 0x0010
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#define ORB_CTRL0_MASK_SSIC 0x0008
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#define ORB_CTRL0_MASK_C64 0x0002
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#define ORB_CTRL0_MASK_I2K 0x0001
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#define ORB_CTRL0_MASK_INVALID 0x0004
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#define ORB_CTRL1_MASK_ILS 0x80
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#define ORB_CTRL1_MASK_MIDAW 0x40
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#define ORB_CTRL1_MASK_ORBX 0x01
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#define ORB_CTRL1_MASK_INVALID 0x3e
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/* channel command word (type 0) */
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typedef struct CCW0 {
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uint8_t cmd_code;
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uint8_t cda0;
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uint16_t cda1;
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uint8_t flags;
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uint8_t reserved;
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uint16_t count;
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} CCW0;
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QEMU_BUILD_BUG_MSG(sizeof(CCW0) != 8, "size of CCW0 is wrong");
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/* channel command word (type 1) */
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typedef struct CCW1 {
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uint8_t cmd_code;
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uint8_t flags;
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uint16_t count;
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uint32_t cda;
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} CCW1;
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QEMU_BUILD_BUG_MSG(sizeof(CCW1) != 8, "size of CCW1 is wrong");
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#define CCW_FLAG_DC 0x80
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#define CCW_FLAG_CC 0x40
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#define CCW_FLAG_SLI 0x20
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#define CCW_FLAG_SKIP 0x10
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#define CCW_FLAG_PCI 0x08
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#define CCW_FLAG_IDA 0x04
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#define CCW_FLAG_SUSPEND 0x02
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#define CCW_FLAG_MIDA 0x01
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#define CCW_CMD_NOOP 0x03
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#define CCW_CMD_BASIC_SENSE 0x04
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#define CCW_CMD_TIC 0x08
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#define CCW_CMD_SENSE_ID 0xe4
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typedef struct CRW {
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uint16_t flags;
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uint16_t rsid;
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} CRW;
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QEMU_BUILD_BUG_MSG(sizeof(CRW) != 4, "size of CRW is wrong");
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#define CRW_FLAGS_MASK_S 0x4000
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#define CRW_FLAGS_MASK_R 0x2000
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#define CRW_FLAGS_MASK_C 0x1000
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#define CRW_FLAGS_MASK_RSC 0x0f00
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#define CRW_FLAGS_MASK_A 0x0080
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#define CRW_FLAGS_MASK_ERC 0x003f
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#define CRW_ERC_EVENT 0x00 /* event information pending */
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#define CRW_ERC_AVAIL 0x01 /* available */
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#define CRW_ERC_INIT 0x02 /* initialized */
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#define CRW_ERC_TERROR 0x03 /* temporary error */
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#define CRW_ERC_IPI 0x04 /* installed parm initialized */
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#define CRW_ERC_TERM 0x05 /* terminal */
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#define CRW_ERC_PERRN 0x06 /* perm. error, facility not init */
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#define CRW_ERC_PERRI 0x07 /* perm. error, facility init */
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#define CRW_ERC_PMOD 0x08 /* installed parameters modified */
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#define CRW_ERC_IPR 0x0A /* installed parameters restored */
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#define CRW_RSC_SUBCH 0x3
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#define CRW_RSC_CHP 0x4
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#define CRW_RSC_CSS 0xb
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/* I/O interruption code */
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typedef struct IOIntCode {
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uint32_t subsys_id;
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uint32_t intparm;
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uint32_t interrupt_id;
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} QEMU_PACKED IOIntCode;
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/* schid disintegration */
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#define IOINST_SCHID_ONE(_schid) ((_schid & 0x00010000) >> 16)
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#define IOINST_SCHID_M(_schid) ((_schid & 0x00080000) >> 19)
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#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24)
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#define IOINST_SCHID_SSID(_schid) ((_schid & 0x00060000) >> 17)
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#define IOINST_SCHID_NR(_schid) (_schid & 0x0000ffff)
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#define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 27)
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#define ISC_TO_ISC_BITS(_isc) ((0x80 >> _isc) << 24)
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#define IO_INT_WORD_AI 0x80000000
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int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
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int *schid);
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#endif
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