Files
qemu/target/riscv/insn_trans
Max Chou b48381b1ee target/riscv: Set vdata.vm field for vector load/store whole register instructions
The vm field of the vector load/store whole register instruction's
encoding is 1.
The helper function of the vector load/store whole register instructions
may need the vdata.vm field to do some optimizations.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-11-07 08:21:14 +10:00
..
2023-10-03 08:01:02 -07:00