49157207c0
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
138 lines
4.8 KiB
C
138 lines
4.8 KiB
C
/*
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* B-L475E-IOT01A Discovery Kit machine
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* (B-L475E-IOT01A IoT Node)
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*
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* Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* This work is heavily inspired by the netduinoplus2 by Alistair Francis.
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* Original code is licensed under the MIT License:
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*/
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/*
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* The reference used is the STMicroElectronics UM2153 User manual
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* Discovery kit for IoT node, multi-channel communication with STM32L4.
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* https://www.st.com/en/evaluation-tools/b-l475e-iot01a.html#documentation
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "hw/arm/boot.h"
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#include "hw/core/split-irq.h"
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#include "hw/arm/stm32l4x5_soc.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/display/dm163.h"
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/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
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/*
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* There are actually 14 input pins in the DM163 device.
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* Here the DM163 input pin EN isn't connected to the STM32L4x5
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* GPIOs as the IM120417002 colors shield doesn't actually use
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* this pin to drive the RGB matrix.
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*/
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#define NUM_DM163_INPUTS 13
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static const unsigned dm163_input[NUM_DM163_INPUTS] = {
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1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */
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0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */
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0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */
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0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */
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0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */
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0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */
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1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */
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0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */
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0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */
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1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */
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2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */
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2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */
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2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */
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};
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#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
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OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
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typedef struct Bl475eMachineState {
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MachineState parent_obj;
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Stm32l4x5SocState soc;
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SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
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DM163State dm163;
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} Bl475eMachineState;
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static void bl475e_init(MachineState *machine)
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{
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Bl475eMachineState *s = B_L475E_IOT01A(machine);
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const Stm32l4x5SocClass *sc;
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DeviceState *dev, *gpio_out_splitter;
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unsigned gpio, pin;
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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TYPE_STM32L4X5XG_SOC);
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sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
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sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
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armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
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sc->flash_size);
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if (object_class_by_name(TYPE_DM163)) {
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object_initialize_child(OBJECT(machine), "dm163",
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&s->dm163, TYPE_DM163);
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dev = DEVICE(&s->dm163);
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qdev_realize(dev, NULL, &error_abort);
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for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
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object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
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&s->gpio_splitters[i], TYPE_SPLIT_IRQ);
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gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
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qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
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qdev_realize(gpio_out_splitter, NULL, &error_fatal);
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qdev_connect_gpio_out(gpio_out_splitter, 0,
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qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
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qdev_connect_gpio_out(gpio_out_splitter, 1,
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qdev_get_gpio_in(dev, i));
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gpio = dm163_input[i] / GPIO_NUM_PINS;
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pin = dm163_input[i] % GPIO_NUM_PINS;
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qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
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qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
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}
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}
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}
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static void bl475e_machine_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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static const char *machine_valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m4"),
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NULL
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};
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mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
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mc->init = bl475e_init;
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mc->valid_cpu_types = machine_valid_cpu_types;
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/* SRAM pre-allocated as part of the SoC instantiation */
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mc->default_ram_size = 0;
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}
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static const TypeInfo bl475e_machine_type[] = {
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{
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.name = TYPE_B_L475E_IOT01A,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(Bl475eMachineState),
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.class_init = bl475e_machine_init,
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}
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};
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DEFINE_TYPES(bl475e_machine_type)
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