Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>
		
			
				
	
	
		
			371 lines
		
	
	
		
			11 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			371 lines
		
	
	
		
			11 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  qemu user cpu loop
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|  *
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|  *  Copyright (c) 2003-2008 Fabrice Bellard
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|  *
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|  *  This program is free software; you can redistribute it and/or modify
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|  *  it under the terms of the GNU General Public License as published by
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|  *  the Free Software Foundation; either version 2 of the License, or
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|  *  (at your option) any later version.
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|  *
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|  *  This program is distributed in the hope that it will be useful,
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|  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  *  GNU General Public License for more details.
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|  *
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|  *  You should have received a copy of the GNU General Public License
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|  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #include "qemu/osdep.h"
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| #include "qemu.h"
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| #include "user-internals.h"
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| #include "cpu_loop-common.h"
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| #include "signal-common.h"
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| 
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| #define SPARC64_STACK_BIAS 2047
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| 
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| //#define DEBUG_WIN
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| 
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| /* WARNING: dealing with register windows _is_ complicated. More info
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|    can be found at http://www.sics.se/~psm/sparcstack.html */
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| static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
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| {
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|     index = (index + cwp * 16) % (16 * env->nwindows);
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|     /* wrap handling : if cwp is on the last window, then we use the
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|        registers 'after' the end */
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|     if (index < 8 && env->cwp == env->nwindows - 1)
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|         index += 16 * env->nwindows;
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|     return index;
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| }
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| 
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| /* save the register window 'cwp1' */
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| static inline void save_window_offset(CPUSPARCState *env, int cwp1)
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| {
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|     unsigned int i;
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|     abi_ulong sp_ptr;
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| 
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|     sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
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| #ifdef TARGET_SPARC64
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|     if (sp_ptr & 3)
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|         sp_ptr += SPARC64_STACK_BIAS;
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| #endif
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| #if defined(DEBUG_WIN)
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|     printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
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|            sp_ptr, cwp1);
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| #endif
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|     for(i = 0; i < 16; i++) {
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|         /* FIXME - what to do if put_user() fails? */
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|         put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
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|         sp_ptr += sizeof(abi_ulong);
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|     }
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| }
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| 
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| static void save_window(CPUSPARCState *env)
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| {
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| #ifndef TARGET_SPARC64
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|     unsigned int new_wim;
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|     new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
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|         ((1LL << env->nwindows) - 1);
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|     save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
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|     env->wim = new_wim;
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| #else
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|     /*
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|      * cansave is zero if the spill trap handler is triggered by `save` and
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|      * nonzero if triggered by a `flushw`
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|      */
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|     save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
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|     env->cansave++;
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|     env->canrestore--;
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| #endif
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| }
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| 
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| static void restore_window(CPUSPARCState *env)
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| {
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| #ifndef TARGET_SPARC64
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|     unsigned int new_wim;
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| #endif
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|     unsigned int i, cwp1;
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|     abi_ulong sp_ptr;
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| 
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| #ifndef TARGET_SPARC64
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|     new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
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|         ((1LL << env->nwindows) - 1);
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| #endif
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| 
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|     /* restore the invalid window */
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|     cwp1 = cpu_cwp_inc(env, env->cwp + 1);
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|     sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
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| #ifdef TARGET_SPARC64
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|     if (sp_ptr & 3)
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|         sp_ptr += SPARC64_STACK_BIAS;
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| #endif
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| #if defined(DEBUG_WIN)
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|     printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
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|            sp_ptr, cwp1);
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| #endif
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|     for(i = 0; i < 16; i++) {
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|         /* FIXME - what to do if get_user() fails? */
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|         get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
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|         sp_ptr += sizeof(abi_ulong);
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|     }
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| #ifdef TARGET_SPARC64
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|     env->canrestore++;
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|     if (env->cleanwin < env->nwindows - 1)
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|         env->cleanwin++;
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|     env->cansave--;
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| #else
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|     env->wim = new_wim;
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| #endif
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| }
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| 
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| static void flush_windows(CPUSPARCState *env)
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| {
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|     int offset, cwp1;
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| 
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|     offset = 1;
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|     for(;;) {
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|         /* if restore would invoke restore_window(), then we can stop */
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|         cwp1 = cpu_cwp_inc(env, env->cwp + offset);
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| #ifndef TARGET_SPARC64
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|         if (env->wim & (1 << cwp1))
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|             break;
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| #else
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|         if (env->canrestore == 0)
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|             break;
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|         env->cansave++;
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|         env->canrestore--;
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| #endif
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|         save_window_offset(env, cwp1);
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|         offset++;
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|     }
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|     cwp1 = cpu_cwp_inc(env, env->cwp + 1);
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| #ifndef TARGET_SPARC64
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|     /* set wim so that restore will reload the registers */
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|     env->wim = 1 << cwp1;
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| #endif
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| #if defined(DEBUG_WIN)
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|     printf("flush_windows: nb=%d\n", offset - 1);
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| #endif
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| }
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| 
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| static void next_instruction(CPUSPARCState *env)
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| {
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|     env->pc = env->npc;
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|     env->npc = env->npc + 4;
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| }
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| 
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| static uint32_t do_getcc(CPUSPARCState *env)
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| {
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| #ifdef TARGET_SPARC64
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|     return cpu_get_ccr(env) & 0xf;
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| #else
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|     return extract32(cpu_get_psr(env), 20, 4);
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| #endif
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| }
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| 
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| static void do_setcc(CPUSPARCState *env, uint32_t icc)
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| {
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| #ifdef TARGET_SPARC64
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|     cpu_put_ccr(env, (cpu_get_ccr(env) & 0xf0) | (icc & 0xf));
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| #else
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|     cpu_put_psr(env, deposit32(cpu_get_psr(env), 20, 4, icc));
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| #endif
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| }
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| 
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| static uint32_t do_getpsr(CPUSPARCState *env)
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| {
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| #ifdef TARGET_SPARC64
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|     const uint64_t TSTATE_CWP = 0x1f;
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|     const uint64_t TSTATE_ICC = 0xfull << 32;
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|     const uint64_t TSTATE_XCC = 0xfull << 36;
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|     const uint32_t PSR_S      = 0x00000080u;
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|     const uint32_t PSR_V8PLUS = 0xff000000u;
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|     uint64_t tstate = sparc64_tstate(env);
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| 
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|     /* See <asm/psrcompat.h>, tstate_to_psr. */
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|     return ((tstate & TSTATE_CWP)                   |
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|             PSR_S                                   |
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|             ((tstate & TSTATE_ICC) >> 12)           |
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|             ((tstate & TSTATE_XCC) >> 20)           |
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|             PSR_V8PLUS);
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| #else
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|     return (cpu_get_psr(env) & (PSR_ICC | PSR_CWP)) | PSR_S;
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| #endif
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| }
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| 
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| /* Avoid ifdefs below for the abi32 and abi64 paths. */
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| #ifdef TARGET_ABI32
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| #define TARGET_TT_SYSCALL  (TT_TRAP + 0x10) /* t_linux */
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| #else
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| #define TARGET_TT_SYSCALL  (TT_TRAP + 0x6d) /* tl0_linux64 */
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| #endif
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| 
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| /* Avoid ifdefs below for the v9 and pre-v9 hw traps. */
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| #ifdef TARGET_SPARC64
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| #define TARGET_TT_SPILL  TT_SPILL
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| #define TARGET_TT_FILL   TT_FILL
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| #else
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| #define TARGET_TT_SPILL  TT_WIN_OVF
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| #define TARGET_TT_FILL   TT_WIN_UNF
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| #endif
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| 
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| void cpu_loop (CPUSPARCState *env)
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| {
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|     CPUState *cs = env_cpu(env);
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|     int trapnr;
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|     abi_long ret;
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| 
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|     while (1) {
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|         cpu_exec_start(cs);
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|         trapnr = cpu_exec(cs);
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|         cpu_exec_end(cs);
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|         process_queued_cpu_work(cs);
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| 
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|         switch (trapnr) {
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|         case TARGET_TT_SYSCALL:
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|             ret = do_syscall (env, env->gregs[1],
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|                               env->regwptr[0], env->regwptr[1],
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|                               env->regwptr[2], env->regwptr[3],
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|                               env->regwptr[4], env->regwptr[5],
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|                               0, 0);
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|             if (ret == -QEMU_ERESTARTSYS || ret == -QEMU_ESIGRETURN) {
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|                 break;
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|             }
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|             if ((abi_ulong)ret >= (abi_ulong)(-515)) {
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|                 set_syscall_C(env, 1);
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|                 ret = -ret;
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|             } else {
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|                 set_syscall_C(env, 0);
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|             }
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|             env->regwptr[0] = ret;
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|             /* next instruction */
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|             env->pc = env->npc;
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|             env->npc = env->npc + 4;
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|             break;
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| 
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|         case TT_TRAP + 0x01: /* breakpoint */
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|         case EXCP_DEBUG:
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|             force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
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|             break;
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| 
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|         case TT_TRAP + 0x02: /* div0 */
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|         case TT_DIV_ZERO:
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|             force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
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|             break;
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| 
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|         case TT_TRAP + 0x03: /* flush windows */
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|             flush_windows(env);
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|             next_instruction(env);
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|             break;
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| 
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|         case TT_TRAP + 0x20: /* getcc */
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|             env->gregs[1] = do_getcc(env);
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|             next_instruction(env);
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|             break;
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|         case TT_TRAP + 0x21: /* setcc */
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|             do_setcc(env, env->gregs[1]);
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|             next_instruction(env);
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|             break;
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|         case TT_TRAP + 0x22: /* getpsr */
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|             env->gregs[1] = do_getpsr(env);
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|             next_instruction(env);
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|             break;
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| 
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| #ifdef TARGET_SPARC64
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|         case TT_TRAP + 0x6e:
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|             flush_windows(env);
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|             sparc64_get_context(env);
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|             break;
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|         case TT_TRAP + 0x6f:
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|             flush_windows(env);
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|             sparc64_set_context(env);
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|             break;
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| #endif
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| 
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|         case TARGET_TT_SPILL: /* window overflow */
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|             save_window(env);
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|             break;
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|         case TARGET_TT_FILL:  /* window underflow */
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|             restore_window(env);
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|             break;
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| 
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|         case TT_FP_EXCP:
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|             {
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|                 int code = TARGET_FPE_FLTUNK;
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|                 target_ulong fsr = cpu_get_fsr(env);
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| 
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|                 if ((fsr & FSR_FTT_MASK) == FSR_FTT_IEEE_EXCP) {
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|                     if (fsr & FSR_NVC) {
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|                         code = TARGET_FPE_FLTINV;
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|                     } else if (fsr & FSR_OFC) {
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|                         code = TARGET_FPE_FLTOVF;
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|                     } else if (fsr & FSR_UFC) {
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|                         code = TARGET_FPE_FLTUND;
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|                     } else if (fsr & FSR_DZC) {
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|                         code = TARGET_FPE_FLTDIV;
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|                     } else if (fsr & FSR_NXC) {
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|                         code = TARGET_FPE_FLTRES;
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|                     }
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|                 }
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|                 force_sig_fault(TARGET_SIGFPE, code, env->pc);
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|             }
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|             break;
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| 
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|         case EXCP_INTERRUPT:
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|             /* just indicate that signals should be handled asap */
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|             break;
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|         case TT_ILL_INSN:
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|             force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc);
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|             break;
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|         case TT_PRIV_INSN:
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|             force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc);
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|             break;
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|         case TT_TOVF:
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|             force_sig_fault(TARGET_SIGEMT, TARGET_EMT_TAGOVF, env->pc);
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|             break;
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| #ifdef TARGET_SPARC64
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|         case TT_PRIV_ACT:
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|             /* Note do_privact defers to do_privop. */
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|             force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc);
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|             break;
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| #else
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|         case TT_NCP_INSN:
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|             force_sig_fault(TARGET_SIGILL, TARGET_ILL_COPROC, env->pc);
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|             break;
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|         case TT_UNIMP_FLUSH:
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|             next_instruction(env);
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|             break;
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| #endif
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|         case EXCP_ATOMIC:
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|             cpu_exec_step_atomic(cs);
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|             break;
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|         default:
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|             /*
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|              * Most software trap numbers vector to BAD_TRAP.
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|              * Handle anything not explicitly matched above.
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|              */
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|             if (trapnr >= TT_TRAP && trapnr <= TT_TRAP + 0x7f) {
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|                 force_sig_fault(TARGET_SIGILL, ILL_ILLTRP, env->pc);
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|                 break;
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|             }
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|             fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
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|             cpu_dump_state(cs, stderr, 0);
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|             exit(EXIT_FAILURE);
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|         }
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|         process_pending_signals (env);
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|     }
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| }
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| 
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| void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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| {
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|     int i;
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|     env->pc = regs->pc;
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|     env->npc = regs->npc;
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|     env->y = regs->y;
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|     for(i = 0; i < 8; i++)
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|         env->gregs[i] = regs->u_regs[i];
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|     for(i = 0; i < 8; i++)
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|         env->regwptr[i] = regs->u_regs[i + 8];
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| }
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