Kito Cheng 620455350a target/riscv: Fix wrong expanding for c.fswsp ...

base register is no rs1 not rs2 for fsw.

Signed-off-by: Kito Cheng <kito.cheng@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-03-26 03:17:30 -07:00

..

trans_privileged.inc.c

target/riscv: Convert RV priv insns to decodetree

2019-03-13 10:34:06 +01:00

trans_rva.inc.c

target/riscv: Convert RV64A insns to decodetree

2019-03-13 10:34:06 +01:00

trans_rvc.inc.c

target/riscv: Fix wrong expanding for c.fswsp

2019-03-26 03:17:30 -07:00

trans_rvd.inc.c

target/riscv: Convert RV64D insns to decodetree

2019-03-13 10:34:06 +01:00

trans_rvf.inc.c

target/riscv: Convert RV64F insns to decodetree

2019-03-13 10:34:06 +01:00

trans_rvi.inc.c

target/riscv: Rename trans_arith to gen_arith

2019-03-13 10:40:50 +01:00

trans_rvm.inc.c

target/riscv: Zero extend the inputs of divuw and remuw

2019-03-22 00:26:39 -07:00