30efbf330a
QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
/*
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* sifive System-on-Chip general purpose input/output register definition
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*
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* Copyright 2019 AdaCore
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*
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* Base on nrf51_gpio.c:
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*
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* Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef SIFIVE_GPIO_H
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#define SIFIVE_GPIO_H
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#include "hw/sysbus.h"
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#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
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#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
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#define SIFIVE_GPIO_PINS 32
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#define SIFIVE_GPIO_SIZE 0x100
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#define SIFIVE_GPIO_REG_VALUE 0x000
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#define SIFIVE_GPIO_REG_INPUT_EN 0x004
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#define SIFIVE_GPIO_REG_OUTPUT_EN 0x008
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#define SIFIVE_GPIO_REG_PORT 0x00C
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#define SIFIVE_GPIO_REG_PUE 0x010
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#define SIFIVE_GPIO_REG_DS 0x014
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#define SIFIVE_GPIO_REG_RISE_IE 0x018
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#define SIFIVE_GPIO_REG_RISE_IP 0x01C
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#define SIFIVE_GPIO_REG_FALL_IE 0x020
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#define SIFIVE_GPIO_REG_FALL_IP 0x024
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#define SIFIVE_GPIO_REG_HIGH_IE 0x028
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#define SIFIVE_GPIO_REG_HIGH_IP 0x02C
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#define SIFIVE_GPIO_REG_LOW_IE 0x030
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#define SIFIVE_GPIO_REG_LOW_IP 0x034
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#define SIFIVE_GPIO_REG_IOF_EN 0x038
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#define SIFIVE_GPIO_REG_IOF_SEL 0x03C
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#define SIFIVE_GPIO_REG_OUT_XOR 0x040
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typedef struct SIFIVEGPIOState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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qemu_irq irq[SIFIVE_GPIO_PINS];
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qemu_irq output[SIFIVE_GPIO_PINS];
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uint32_t value; /* Actual value of the pin */
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uint32_t input_en;
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uint32_t output_en;
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uint32_t port; /* Pin value requested by the user */
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uint32_t pue;
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uint32_t ds;
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uint32_t rise_ie;
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uint32_t rise_ip;
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uint32_t fall_ie;
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uint32_t fall_ip;
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uint32_t high_ie;
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uint32_t high_ip;
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uint32_t low_ie;
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uint32_t low_ip;
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uint32_t iof_en;
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uint32_t iof_sel;
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uint32_t out_xor;
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uint32_t in;
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uint32_t in_mask;
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} SIFIVEGPIOState;
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#endif
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