f8319038daFix typo in changes and carry over a change from SLFO to devel:gcc (but so that gold remains enabled on Factory for now) - pr33029.patch: Fix crash in assembler with -gdwarf-5Michael Matz2025-07-17 13:10:39 +00:00
f499f1acf5- binutils-gold is gone for good - remove support for our unsupported architectures from the enterprise codestreams (alpha, avr, pru, epiphany, hppa, ia64, m68k, mips, rx, sh4 sparc, xtensa)Michael Matz2025-03-25 14:36:17 +00:00
66c9b49144- Update to current 2.44: * riscv - disassembly now supports -M,max * nios2 - support dropped except in readelf * assembler: - x86: add support for AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32 and AMX-TRANSPOSE, MOVRS, PHE2, RNG2, GMI, MSR_IMM instructions - x86: add support for Intel AVX10.2 and SM4 AVX10.2 extensions - aarch64: SME and SVE non-widening BFloat16 instructions - riscv: various standard and vendor extensions added: Zicfiss v1.0, Zicfilp v1.0, Zcmp v1.0, Zcmt v1.0, Smrnmi v1.0, S[sm]dbltrp v1.0 and S[sm]ctr v1.0; CORE-V: xcvbitmanip v1.0 and xcvsimd v1.0; SiFive: xsfvqmaccdod v1.0, xsfvqmaccqoqv1.0 and xsfvfnrclipxfqf v1.0 * linker: - loongarch: changed default max page size from 16KiB to 64KiB - add support for mixed LTO and non-LTO code in relocatable output - add --image-base=<ADDR> to behave like -Ttext-segment for compatibility with LLD - Accept percent-encoded and %[string] encoded JSON payload with --package-metadata - binutils-gold is gone for good.Michael Matz2025-03-24 16:30:48 +00:00
0073239164- Do not build binutils-gold for openSUSE Factory or SLFO.Richard Biener2025-02-13 10:20:31 +00:00
4b78165cf7Accepting request 1237516 from devel:gccAna Guerrero2025-01-15 16:42:31 +00:00
872ccfe028- Enable multitarget build on loongarch64Michael Matz2025-01-13 15:24:18 +00:00
0b92143ab3Accepting request 1235669 from devel:gccAna Guerrero2025-01-09 14:04:09 +00:00
ea6705f235- Unset SUSE_ZNOW while running testsuite, many tests cannot copeMichael Matz2025-01-07 16:15:39 +00:00
1100ed340eAccepting request 1229830 from devel:gccAna Guerrero2024-12-11 20:01:22 +00:00
37d03cdb94- Disable zstd-by-default again (needs adjustments in at least golang,llvm15,llvm17 first) - Add binutils-fix-branch.diff. - Check non-changing of flex/bison inputs only after applying branch and fix-branch diffs.Michael Matz2024-12-09 15:54:38 +00:00
89ba785707- Update to current 2.43.1 branch [PED-10254, PED-10306]: * s390 - Add arch15 instructions * various fixes from upstream: PR32153, PR32171, PR32189, PR32196, PR32191, PR32109, PR32372, PR32387 - Adjusted binutils-2.43-branch.diff.gz.Michael Matz2024-12-09 14:59:58 +00:00
38e0c73256- drop ld-relro.diff (relro is the default for some time) and it warns on avr spuriously (bsc#1233520)Richard Biener2024-11-26 10:31:08 +00:00
5b00f2f6a7Accepting request 1199785 from home:martinliska:branches:devel:gccMichael Matz2024-10-14 13:27:39 +00:00
09caadc22bBlaeh, also rebase the patches for old codestreams * Rebased ld-relro.diff and binutils-revert-rela.diff.Michael Matz2024-08-06 14:51:59 +00:00
f32da6f20f- Update to version 2.43: * new .base64 pseudo-op, allowing base64 encoded data as strings * Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF (APX_F now fully supported) * x86 Intel syntax now warns about more mnemonic suffixes * macros and .irp/.irpc/.rept bodies can use \+ to get at number of times the macro/body was executed * aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2 * s390: base register operand in D(X,B) and D(L,B) can now be omitted (ala 'D(X,)'); warn when register type doesn't match operand type (use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust) * riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at version 1.0; remove support for assembly of privileged spec 1.9.1 (linking support remains) * arm: remove support for some old co-processors: Maverick and FPA * mips: '--trap' now causes either trap or breakpoint instructions to be emitted as per current ISA, instead of always using trap insn and failing when current ISA was incompatible with that * LoongArch: accept .option pseudo-op for fine-grained control of assembly code options; add support for DT_RELR * readelf: now displays RELR relocations in full detail; add -j/--display-section to show just those section(s) content according to their type * objdump/readelf now dump also .eh_frame_hdr (when present) when dumping .eh_frame * gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors; add minimal support for riscv * linker:Michael Matz2024-08-06 14:38:53 +00:00
a535d8569eAccepting request 1183197 from devel:gccAna Guerrero2024-06-27 13:57:39 +00:00
20c893709dAccepting request 1171312 from devel:gccAna Guerrero2024-05-03 17:44:17 +00:00
25ef655d66Accepting request 1171128 from home:bmwiedemann:branches:devel:gccRichard Biener2024-05-02 09:48:54 +00:00
626fe753e0Accepting request 1149163 from home:dimstar:rpm4.20:bRichard Biener2024-05-02 09:47:03 +00:00
c3a490c0a5Accepting request 1148804 from devel:gccAna Guerrero2024-02-23 15:40:10 +00:00
d8ab355f1aAccepting request 1148803 from home:Andreas_Schwab:riscv:binutilsMichael Matz2024-02-21 16:31:48 +00:00
9bf70195f2Accepting request 1144349 from devel:gccAna Guerrero2024-02-18 19:20:43 +00:00
f343644904- Add binutils-disable-code-arch-error.diff to demote an error about swapped .arch/.code directives to a warning. It happens in the wild.Michael Matz2024-02-05 16:58:24 +00:00
dd7c1c259dUnset SOURCE_DATE_EPOCH for the testsuiteMichael Matz2024-01-31 15:58:56 +00:00
d0f2831079For SLE-12 explicitely add std=gnu++11 to CXX for gold. It's configured and set "correctly" in the gold subdir, but the toplevel passes CXX=g++ down (and that overrides), so hack around this.Michael Matz2024-01-31 14:04:30 +00:00
6d24c45b6eAdjust the patches only applied on old codestreams.Michael Matz2024-01-30 17:07:36 +00:00
98284da2a0- Update to version 2.42: * Add support for many aarch64 extensions: SVE2.1, SME2.1, B16B16, RASv2, LSE128, GCS, CHK, SPECRES2, LRCPC3, THE, ITE, D128, XS and flags to enable them: '+fcma', '+jscvt', '+frintts', '+flagm2', '+rcpc2' and '+wfxt' * Add experimantal support for GAS to synthesize call-frame-info for some hand-written asm (--scfi=experimental) on x86-64. * Add support for more x86-64 extensions: APX: 32 GPRs, NDD, PUSH2/POP2, PUSHP/POPP; USER_MSR, AVX10.1, PBNDKB, SM4, SM3, SHA512, AVX-VNNI-INT16. * Add support for more RISC-V extensions: T-Head v2.3.0, CORE-V v1.0, SiFive VCIX v1.0. * BPF assembler: ';' separates statements now, and does not introduce line comments anymore (use '#' or '//' for this). * x86-64 ld: Add '-z mark-plt/-z nomark-plt' to mark PLT entries with dynamic tags. * risc-v ld: Add '--[no-]check-uleb128'. * New linker script directive: REVERSE, to be combined with SORT_BY_NAME or SORT_BY_INIT_PRIORITY, reverses the generated order. * New linker options --warn-execstack-objects (warn only about execstack when input object files request it), and --error-execstack plus --error-rxw-segments to convert the existing warnings into errors. * objdump: Add -Z/--decompress to be used with -s/--full-contents to decompress section contents before displaying. * readelf: Add --extra-sym-info to be used with --symbols (currently prints section name of references section index). * objcopy: Add --set-section-flags for x86_64 to include SHF_X86_64_LARGE. * s390 disassembly: add target-specific disasm option 'insndesc', as in "objdump -M insndesc" to display an instruction description as comment along with the disassembly.Michael Matz2024-01-30 15:49:12 +00:00
e1e98de2a1Accepting request 1124735 from devel:gccAna Guerrero2023-11-10 11:28:45 +00:00
f30534e59c- Add binutils-use-less-memory.diff to be a little nicer to 32bit userspace and huge links. [bsc#1216908]Michael Matz2023-11-09 16:55:17 +00:00
b848c43c43Accepting request 1113839 from home:Andreas_Schwab:FactoryMichael Matz2023-09-27 13:28:24 +00:00
893acf05ad- Add libzstd-devel to Requires of binutils-devel. (bsc#1215341)Michael Matz2023-09-14 12:28:40 +00:00
9ce63b809cupdate branch to b6f6a3ec (fixes a gold powerpc problem in llvm)Michael Matz2023-09-08 13:34:48 +00:00
c052426963- Update to version 2.41: * The MIPS port now supports the Sony Interactive Entertainment Allegrex processor, used with the PlayStation Portable, which implements the MIPS II ISA along with a single-precision FPU and a few implementation-specific integer instructions. * Objdump's --private option can now be used on PE format files to display the fields in the file header and section headers. * New versioned release of libsframe: libsframe.so.1. This release introduces versioned symbols with version node name LIBSFRAME_1.0. This release also updates the ABI in an incompatible way: this includes removal of sframe_get_funcdesc_with_addr API, change in the behavior of sframe_fre_get_ra_offset and sframe_fre_get_fp_offset APIs. * SFrame Version 2 is now the default (and only) format version supported by gas, ld, readelf and objdump. * Add command-line option, --strip-section-headers, to objcopy and strip to remove ELF section header from ELF file. * The RISC-V port now supports the following new standard extensions: - Zicond (conditional zero instructions) - Zfa (additional floating-point instructions) - Zvbb, Zvbc, Zvkg, Zvkned, Zvknh[ab], Zvksed, Zvksh, Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvkg, Zvkt (vector crypto instructions) * The RISC-V port now supports the following vendor-defined extensions: - XVentanaCondOps * Add support for Intel FRED, LKGS and AMX-COMPLEX instructions. * A new .insn directive is recognized by x86 gas. * Add SME2 support to the AArch64 port. * The linker now accepts a command line option of --remap-inputs <PATTERN>=<FILE> to relace any input file that matches <PATTERN> with <FILE>. In addition the option --remap-inputs-file=<FILE> can be used to specify a file containing any number of these remapping directives.Michael Matz2023-08-16 15:16:34 +00:00
6e3ed92d9c- Enable bpf-none cross target and add bpf-none to the multitarget set of supported targets.Richard Biener2023-03-16 14:55:37 +00:00
c1f5f1a167- Disable packed-relative-relocs for old codestreams. They generate buggy relocations when binutils-revert-rela.diff is active. [bsc#1206556]Michael Matz2023-03-08 15:34:27 +00:00
2580f878fbAccepting request 1060005 from home:dirkmueller:FactoryMichael Matz2023-01-20 17:08:10 +00:00
f3d315cc8dMention all the various duplicated tracker entries. Implements [jsc#SLE-25046, jsc#PED-2029, jsc#PED-2035, jsc#PED-2033, jsc#PED-2030, jsc#PED-2038, jsc#PED-2032, jsc#PED-2034, jsc#PED-2031, jsc#SLE-25047]Michael Matz2022-11-02 16:28:43 +00:00
2489107f56Another SLE patch and updating CVE mentions in .changesMichael Matz2022-10-25 15:43:19 +00:00
278e829c00Accepting request 1031143 from home:Andreas_Schwab:FactoryMichael Matz2022-10-25 14:40:05 +00:00
b1a0c6a5a8- SLE toolchain update of binutils. Update to 2.39 from 2.37, which means obsoleting and hence removing these patches: binutils-add-efi-aarch64-1.diff, binutils-add-efi-aarch64-2.diff, binutils-add-efi-aarch64-3.diff, binutils-fix-keepdebug.diff, binutils-add-z16-name.diff. (Fake entry from SLE for tracking purposes:) - For building shim 15.6~rc1 (and later versions) aarch64 image, objcopy needs to support efi-app-aarch64 target. (bsc#1198458) Adds binutils-add-efi-aarch64-1.diff, binutils-add-efi-aarch64-2.diff, binutils-add-efi-aarch64-3.diff .Michael Matz2022-10-17 15:18:05 +00:00
cfaae36524- Add binutils-revert-rela.diff to revert back to old behaviour of not ignoring the in-section content of to be relocated fields on x86-64, even though that's a RELA architecture. Compatibility with buggy object files generated by old tools. [bsc#1198422] (forward port from SLE)Michael Matz2022-10-17 15:04:37 +00:00
9460b44a5cThe last change was premature, 2.39 isn't actually affected by the problem, it was introduced in one of the prerequisite patches, remove all traces of the change.Michael Matz2022-09-01 11:57:45 +00:00
8d8118647c- Add binutils-pr29370.diff and their prerequisites binutils-pr29370-pre1.diff and binutils-pr29370-pre2.diff for PR29370, aka CVE-2022-38128 [bsc#1203016]Michael Matz2022-09-01 11:54:53 +00:00