Richard Biener
0eb78911bb
issue which is CVE-2017-11671. [bnc#1050947] OBS-URL: https://build.opensuse.org/package/show/devel:gcc/gcc48?expand=0&rev=211
81 lines
2.2 KiB
Diff
81 lines
2.2 KiB
Diff
CVE-2017-11671
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2017-03-25 Uros Bizjak <ubizjak@gmail.com>
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PR target/80180
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* config/i386/i386.c (ix86_expand_builtin)
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<IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Do not expand arg0 between
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flags reg setting and flags reg using instructions.
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<IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Ditto. Use non-flags reg
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clobbering instructions to zero extend op2.
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Index: gcc/config/i386/i386.c
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===================================================================
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--- gcc/config/i386/i386.c (revision 246478)
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+++ gcc/config/i386/i386.c (revision 246479)
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@@ -39533,9 +39533,6 @@ ix86_expand_builtin (tree exp, rtx targe
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mode0 = DImode;
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rdrand_step:
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- op0 = gen_reg_rtx (mode0);
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- emit_insn (GEN_FCN (icode) (op0));
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-
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arg0 = CALL_EXPR_ARG (exp, 0);
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op1 = expand_normal (arg0);
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if (!address_operand (op1, VOIDmode))
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@@ -39543,6 +39540,10 @@ rdrand_step:
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op1 = convert_memory_address (Pmode, op1);
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op1 = copy_addr_to_reg (op1);
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}
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+
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+ op0 = gen_reg_rtx (mode0);
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+ emit_insn (GEN_FCN (icode) (op0));
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+
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emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
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op1 = gen_reg_rtx (SImode);
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@@ -39551,8 +39552,20 @@ rdrand_step:
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/* Emit SImode conditional move. */
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if (mode0 == HImode)
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{
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- op2 = gen_reg_rtx (SImode);
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- emit_insn (gen_zero_extendhisi2 (op2, op0));
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+ if (TARGET_ZERO_EXTEND_WITH_AND
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+ && optimize_function_for_speed_p (cfun))
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+ {
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+ op2 = force_reg (SImode, const0_rtx);
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+
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+ emit_insn (gen_movstricthi
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+ (gen_lowpart (HImode, op2), op0));
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+ }
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+ else
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+ {
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+ op2 = gen_reg_rtx (SImode);
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+
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+ emit_insn (gen_zero_extendhisi2 (op2, op0));
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+ }
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}
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else if (mode0 == SImode)
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op2 = op0;
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@@ -39584,9 +39597,6 @@ rdrand_step:
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mode0 = DImode;
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rdseed_step:
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- op0 = gen_reg_rtx (mode0);
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- emit_insn (GEN_FCN (icode) (op0));
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-
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arg0 = CALL_EXPR_ARG (exp, 0);
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op1 = expand_normal (arg0);
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if (!address_operand (op1, VOIDmode))
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@@ -39594,6 +39604,10 @@ rdseed_step:
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op1 = convert_memory_address (Pmode, op1);
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op1 = copy_addr_to_reg (op1);
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}
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+
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+ op0 = gen_reg_rtx (mode0);
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+ emit_insn (GEN_FCN (icode) (op0));
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+
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emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
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op2 = gen_reg_rtx (QImode);
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