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Curate and trim changelog for size
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cpuid.changes
133
cpuid.changes
@ -9,11 +9,8 @@ Mon Aug 5 16:05:55 UTC 2024 - Valentin Lefebvre <valentin.lefebvre@suse.com>
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This should correctly identify retail Zen 5 Ryzen's. This also
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corrects some stepping bugs from the Zen 1 era.
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- Update to release 20240709
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* cpuid.c: Added 6/eax IA32_HWP_CTL MSR supported.
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* cpuid.c: Added 7/2/edx MONITOR perf unaffected by tbl overflow.
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* cpuid.c: Added synth decoding for Hygon Dhyana B1 & C2. Still no
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information on a uarch name for these, so decode_uarch_hygon() remains
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silent for them.
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information on a uarch name for these.
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* cpuid.c: Added uarch synth decoding for (0,6),(5,5),11 Cooper Lake.
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The synth decoding was already present. Its absence from
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decode_uarch_intel was just an oversight.
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@ -21,45 +18,12 @@ Mon Aug 5 16:05:55 UTC 2024 - Valentin Lefebvre <valentin.lefebvre@suse.com>
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1/4 (zero fallback). This is meant for old, incomplete cpuid -r
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dumps, but even for hand-crafted dumps, determining 0 cores and then
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dividing by that 0 is unacceptable.
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- Update to release 20240409
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* cpuid.c: Added 0x8000000a/edx PMC virtualization.
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* cpuid.c: Added 0x8000000a/edx idle HLT intercept.
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* cpuid.c: Added 0x8000001f/eax PMC virtual support for SEV-ES/SNP.
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* cpuid.c: Added 0x8000001f/eax mention of SEV-SNP to existing fields.
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* cpuid.c: Added 0x8000001f/eax RMPREAD instruction.
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* cpuid.c: Added 0x8000001f/eax secure AVIC support.
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* cpuid.c: Added 0x8000001f/eax allowed SEV features support.
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* cpuid.c: Added 0x8000001f/eax write to hypervisor in-used allowed.
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* cpuid.c: Added 0x8000001f/eax IBPB on entry support.
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* cpuid.c: Added Siena to (10,15),(10,x) synth decoding, based on 58268
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Arch Overview.
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* cpuid.man: Added 58268: AMD EPYC 8004 Series Architecture Overview.
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* cpuid.c: Added preliminary (10,15),(7,12) Hawk Point synth decoding.
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* cpuid.c: Fixed spelling: EPGR->EGPR (extended GPR's).
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- Update to release 20240330
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* cpuid.c: Added 5/ecx monitorless MWAIT.
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* cpuid.c: Added 7/1/edx user-timer events.
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* cpuid.c: Added 7/1/edx AVX10 instructions.
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* cpuid.c: Added 7/1/edx APX advanced performance extensions.
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* cpuid.c: Added 7/1/edx MWAIT instruction (overrides 1/ecx[3]).
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* cpuid.c: Added Intel-specific print_instr_synth_intel to determine
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presence of MWAIT from 1/ecx and/or 7/1/edx.
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* cpuid.c: Updated 12/n/ecx section property values 1 & 3.
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* cpuid.c: Added 14/0/ebx PTTT processor trace trigger tracing.
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* cpuid.c: Added 14/1/eax number of IA32_RTIT_TRIGGERx_CFG MSRs,
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including D4_IMAGES decoding.
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* cpuid.c: Added 14/1/ecx flags.
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* cpuid.c: Added MINUS24_IMAGES decoding for 0xf/1/eax QoS monitoring
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counter size.
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* cpuid.c: Added 0x23/1 sub-header: Architecture Performance Monitoring
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Extended Counters Supported Bitmaps (0x23/1), and simplified fields.
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* cpuid.c: Added 0x23/2 sub-header: Architecture Performance Monitoring
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Extended Auto Counter Reload (ACR) Bitmaps (0x23/2), expanded on
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existing field descriptions, and added "can cause reloads" fields.
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* cpuid.c: Added 0x24 leaf: Converged Vector ISA.
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* cpuid.c: Added to print_d_n: new XSAVE area: 19 for APX EPGR
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(extended general purpose registers).
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* cpuid.man: Added new Intel 355828 (APX) doc.
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* cpuid.c: Added uarch decoding for (11,15),(1,0), which is mentioned
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with (11,15),(0,0) in the title of 58088 AMD 1Ah Models 00h-0Fh and
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Models 10h-1Fh ACPI v6.5 Porting Guide.
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@ -69,102 +33,9 @@ Mon Aug 5 16:05:55 UTC 2024 - Valentin Lefebvre <valentin.lefebvre@suse.com>
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will use moving forward, or a quirk of engr samples, but checking for
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it is harmless enough.
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- Update to release 20240324
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* cpuid.c: Updated synth decoding for (0,6),(12,15),2 Emerald Rapids
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A1/R1.
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* cpuid.man: Added new Intel docs.
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* cpuid.c: In do_real(), for the 0x1b leaf, add a sanity check to avoid
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infinite recursion if a hypervisor never reports invalid (0) on any
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subleaf. The sanity check checks for a subleaf identical to its
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predecessor, which is not reasonable.
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* cpuid.c: Added synth & uarch decoding for (0,6),(13,13) Clearwater
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Forest.
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* cpuid.c: Updated (0,6),(8,12),1 to include stepping B0, from ILPMDF*
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* cpuid.c: Updated (0,6),(11,15),5 to Raptor Lake stepping H0, based on
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preponderance of evidence.
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* cpuid.c: Added synth decoding for (0,6),(10,10) Core Ultra CPUs.
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* cpuid.c: Updated (0,6),(11,7) to include Core i*-14000. Some CPUs
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having this branding, and it's not clear what's different from the
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Core i*-13000 versions. The steppings don't seem to matter.
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Inspection suggests maybe CET_SSS.
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* cpuid.c: Corrected synth decoding for (10,15),(1,8) Storm Peak: Ryzen
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Threadripper 7000.
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* cpuid.c: Added synth decoding for (10,15),(7,5),2 AMD Ryzen Phoenix F2.
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* cpuid.c: Added very preliminary uarch decoding for (10,15),(6,0) and
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(10,15),(7,0), both Zen 5.
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* cpuid.c: Changed preliminary synth decoding for (0,6),(11,5) to Arrow
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Lake, based on Intel SDE 9.33.0.
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* cpuid.c: Added synth decoding for (0,6),(8,13),0 Tiger Lake-H P0
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stepping.
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* cpuid.c: Added synth decoding for (0,6),(11,13),0 Lunar Lake A0
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stepping.
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* cpuid.c: Changed uarch decoding for (0,6),(13,13) to Darkmont, the
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presumed uarch for Clearwater Forest.
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* cpuid.c: Added 12/1/eax AEX attribute enabled, as described by Scott
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Raynor, Intel.
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* cpuid.c: Added 7/1/eax NMI-source reporting.
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* cpuid.c: Added 7/1/eax INVD prevention after BIOS done.
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* cpuid.c: Renamed 7/1/ebx PKNDKB instruction.
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* cpuid.c: Added 7/1/edx URDMSR, UWRMSR instructions.
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* cpuid.c: Added 0xa/ebx additional events.
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* cpuid.c: Added 0xf/1/eax non-CPU agent features.
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* cpuid.c: For 0xf/0/edx supports L3 cache monitoring, removed
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redundant "QoS".
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* cpuid.c: Renamed print_10_n_{eax,ecx} -> print_10_12_{eax,ecx}.
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* cpuid.c: Added 0x10/0/ebx cache bandwidth allocation supported.
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* cpuid.c: Replaced 0x10/{1,2}/ecx: non-CPU agent support.
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* cpuid.c: Renamed 0x10/{1,2}/ecx: non-contiguous bitmask supported.
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* cpuid.c: Added 0x10/5 Cache Bandwidth Allocation decoding.
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* cpuid.c: Renamed 0x23/0/ebx IA32_PERFEVTSELx EQ bit supported.
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* cpuid.c: Added 0x23/2 ACR counters bitmaps.
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* cpuid.c: Corrected synth decoding for (10,15),(10,x) to EPYC (4th Gen)
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(server CPUs), instead of Ryzen (desktop CPUs).
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* cpuid.c: Added (0,6),(12,12) Panther Lake synth decoding from LX*, but
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left out corresponding uarch decoding which is alls rumors currently:
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maybe Panther Cove, Cougar Cove, or something else.
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* cpuid.c: Added hypervisor+0xc ebx isolation type new value: TDX (3)
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from LX*.
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* cpuid.c: Added (11,5),(0,0) Zen 5 uarch from LX*.
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* cpuid.c: To decode_uarch_intel, added (0,6),(11,12) & (0,6),(11,13)
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Lion Cove & Skymont as uarch underpinning Lunar Lake.
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* cpuid.c: Added 0x80000021/eax selective branch prediction barrier,
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PRED_CMD[IBPB] flushes branch type preds. They appear to be only
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synthetic flags provided for hypervisor guests!
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* cpuid.c: Added 0x80000021/eax CPU not affected by SRSO flag, from LX*.
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* cpuid.c: Added (10,15),(8&9,0) uarch & synth decoding for AMD Instinct
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MI300, from LKML: https://lkml.org/lkml/2023/7/20/668 patches.
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In the past, Instinct MI* described just the GPU, but they seem to be
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conflating them into a product name here.
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* cpuid.: Added prelim uarch decoding for (11,15),(2,0) & (11,15),(4,0),
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both Zen 5, based on engr samples. No synth decoding yet, because it
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isn't known yet.
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* cpuid.c: Added prelim synth decoding for (0,6),(11,12) Lunar Lake from
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Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def. No uarch decoding, because
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Lunar Lake uarch name is not known yet.
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* cpuid.c: Added prelim synth decoding for (0,6),(9,5) Sapphire Rapids
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from Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def.
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* cpuid.c: Added synth decoding for (0,6),(11,7),0 Raptor Lake A0
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stepping, from Coreboot*.
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* cpuid.c: Added 7/1/eax SHA512, SM3 & SM4 instructions.
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* cpuid.c: Added 7/1/ebx TSE PBNDKB instruction.
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* cpuid.c: Added 7/1/ebx AVX-VNNI-INT16 instructions.
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* cpuid.c: Added 7/1/edx UIRET flexibly updates UIF.
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* cpuid.c: Added 0x1b/2 TSE target.
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* cpuid.c: Corrected sub-leaf walk of leaf 0x1b to stop immediately if
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sub-leaf 0 is invalid.
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* cpuid.c: Added (uarch synth) & (synth) decoding for (0,6),(12,5)
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Arrow Lake based on Lion Cove & Skymont.
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* cpuid.c: Added 0x80000008/ebx IBPB_RET.
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* cpuid.c: Renamed 0x8000000a/edx extended LVT AVIC access changes.
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* cpuid.c: Renamed 0x8000000a/edx guest VMCB addr check.
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* cpuid.c: Added 0x8000000a/edx bus lock threshold.
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* cpuid.c: Renamed several 0x80000020 leaves & fields.
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* cpuid.c: Added 0x80000020/0/ebx assignable bandwidth monitoring
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counters.
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* cpuid.c: Added 0x80000020/0/ebx SDCI allocation enforcement
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* cpuid.c: Added 0x80000020/5 PQoS Assignable Bandwidth Monitoring
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Counters.
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* cpuid.c: Added (synth) decoding for (0,6),(10,10),4 Meteor Lake-M C0
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stepping from Coreboot*
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Core i*-13000 versions.
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-------------------------------------------------------------------
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Wed Jun 21 09:18:20 UTC 2023 - Valentin Lefebvre <valentin.lefebvre@suse.com>
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