From 92fdeabf676f89dc7aaff3b60251d32f0f988b9e2ad85f0bdf48acf45b7d1dd3 Mon Sep 17 00:00:00 2001 From: Jan Engelhardt Date: Fri, 14 Apr 2023 08:56:36 +0000 Subject: [PATCH 1/2] Accepting request 1079377 from home:eeich:branches:utilities - Update to release 20230406: * Fixed bug when interpreting leaf 0xb and 0x1f bit widths: Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1 in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID values. * For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of level & previous levels" to reflect this definition. * Support APIC bit fields for the newest 4 topology layers: module, tile, die, die group. And for the mp version, also the older cu & pkg levels. * Use the extended APIC ID's when available in a variety of leaves. * Support leaf 0xb method for AMD/Hygon. * Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS. * Added 7/1/edx AMX-COMPLEX instructions. * Added 7/2/edx UC-lock disable. * Added 0x10/n/ecx non-contiguous 1s value supported. * Added 0x1c/ecx event logging supported bitmap. * Added 0x23/0/ebx decoding. * Decode 0x80000026/1/ebx core type & native model. * For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match Intel versions in 7/1/eax. * For 0x80000022/ecx, shorten description, show bitmask only in hex. * Update CPUID utility with new feature bits as documented in the AMD Processor Programming Reference for Family 19h and Model 11h: 0x8000000a/edx extended LVT offset fault change 0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC, FsGsKernelGsBaseNonSerializing 0x80000022/ebx number of available UMC PMCs 0x80000022/ecx bitmask representing active UMCs OBS-URL: https://build.opensuse.org/request/show/1079377 OBS-URL: https://build.opensuse.org/package/show/utilities/cpuid?expand=0&rev=45 --- cpuid-20230120.src.tar.gz | 3 - cpuid-20230406.src.tar.gz | 3 + cpuid.changes | 120 +++++++++++++++++++++++++++++++++++++- cpuid.spec | 2 +- 4 files changed, 122 insertions(+), 6 deletions(-) delete mode 100644 cpuid-20230120.src.tar.gz create mode 100644 cpuid-20230406.src.tar.gz diff --git a/cpuid-20230120.src.tar.gz b/cpuid-20230120.src.tar.gz deleted file mode 100644 index 71bbf67..0000000 --- a/cpuid-20230120.src.tar.gz +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:b89b41f8895d0d58fdbb0a54102bb490bc7c5828db2cd15be82d14d19463a579 -size 141652 diff --git a/cpuid-20230406.src.tar.gz b/cpuid-20230406.src.tar.gz new file mode 100644 index 0000000..5bc1af8 --- /dev/null +++ b/cpuid-20230406.src.tar.gz @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f4045de535f30e34e8c012b054ce66f40ac399144d6e3c3896bd80c0deeef1b0 +size 147932 diff --git a/cpuid.changes b/cpuid.changes index 519c7fe..72f36c8 100644 --- a/cpuid.changes +++ b/cpuid.changes @@ -1,7 +1,123 @@ +------------------------------------------------------------------- +Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich + +- Update to release 20230406: + * Fixed bug when interpreting leaf 0xb and 0x1f bit widths: + Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1 + in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID + values. + * For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of + level & previous levels" to reflect this definition. + * Support APIC bit fields for the newest 4 topology + layers: module, tile, die, die group. And for the mp version, also + the older cu & pkg levels. + * Use the extended APIC ID's when available in a variety of leaves. + * Support leaf 0xb method for AMD/Hygon. + * Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS. + * Added 7/1/edx AMX-COMPLEX instructions. + * Added 7/2/edx UC-lock disable. + * Added 0x10/n/ecx non-contiguous 1s value supported. + * Added 0x1c/ecx event logging supported bitmap. + * Added 0x23/0/ebx decoding. + * Decode 0x80000026/1/ebx core type & native model. + * For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match + Intel versions in 7/1/eax. + * For 0x80000022/ecx, shorten description, show bitmask only in + hex. + * Update CPUID utility with new feature bits as documented in + the AMD Processor Programming Reference for Family 19h and Model 11h: + 0x8000000a/edx extended LVT offset fault change + 0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC, + FsGsKernelGsBaseNonSerializing + 0x80000022/ebx number of available UMC PMCs + 0x80000022/ecx bitmask representing active UMCs + * Differentiate preliminary (uarch synth) for (0,6),(10,10); + (0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores + from their Redwood Cove counterparts. + * Added preliminary (synth) & (uarch synth) for (0,6),(12,6) + Lion Cove & Skymont, from LX*. + * Added 12/0/eax SGX ENCLS EUPDATESVN bit. + * Added 0x1f/*/ecx level type value "die group (6)". + * Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D & + E0 steppings from coreboot*. + * Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen + Xeons to Ice Lake-SP. Also, improved decoding for engr samples where + the brand string omits Xeon & Bronze/Silver/Gold/Platinum. + * Improved (synth) decoding for (0,6),(11,14) Intel N-Series. + * Differentiate (synth) & (uarch synth) for (0,6),(11,14) + Alder Lake-N based on core type, much like for other Alder Lake models. + This corrects the cores to Gracemont. As for Golden Cove, perhaps + P-cores never will exist for this model but, if they do, they should + now be decoded correctly. + * Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P. + * Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P. + * Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made + the following (synth) changes: + * Updated (0,6),(3,7),8 Bay Trail with stepping name C0. + * Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping. + * Corrected (0,6),(4,6),1 Crystal Well to C0 stepping. + * Updated (0,6),(4,7),1 Broadwell to include E0 stepping. + * Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable). + * Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable). + * Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable). + * Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0 + steppings. + * Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable). + * Added (0,6),(6,12),1 Ice Lake B0. + * Updated (0,6),(8,6),4 Snow Ridge with stepping B0. + * Updated (0,6),(8,6),5 Snow Ridge with stepping B1. + * Added (0,6),(8,6),1 Lakefield B2/B3 stepping. + * Corrected (0,6),(8,12),1 Tiger Lake stepping to B1. + * Added (0,6),(8,12),2 Tiger Lake C0. + * Added (0,6),(8,14),10 Coffee Lake D0. + * Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping. + * Added (0,6),(8,15) Sapphire Rapids numerous steppings. + * Updated (0,6),(9,12) Jasper Lake with stepping A1. + * Differentiate (0,6),(8,10) Lakefield P-cores from Tremont + E-cores, much as I previously did for Alder Lake & Raptor Lake. + * For known Hybrid chips (Alder Lake, Raptor Lake & Lakefield), + only decode the uarch if it's one of the two known hybrid types. + However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only), + so also decode core type == 0x00 there. + * In the Intel Core era, uarch families are identified only by + the initial uarch in the family. So the family names in {braces}, + which also are uarch names, can be confusing. So, change (synth) and + (uarch synth) for those families to explain the relationships between + the subsequent uarch and the initial uarch, in the form of + "shrink of", "optim of", and the unusual "backport of". + * Added (4th Gen) to the (synth) description of (10,15),(1,*) + AMD EPYC Genoa. + * Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2 + CPUs to claim 4nm process. + * Corrected 7/1/eax fast REP instructions, where I'd left the + REP prefix out of the description. + * Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and + Event Deliver (FRED). + * Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf + 0x23 is valid. + * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based + on sample from bakerlab.org, which I missed on Oct 3 2022, when I + added the (synth) decoding. + * Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family + 19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and + (7,0) Phoenix, based on their respective PPPR's. + * Added very early (synth) decoding for Lunar Lake. There is + no corresponding (uarch synth) decoding, because no name is yet known + for the uarch. + * Added (0,6),(9,10) Alder Lake Core names: i*-12000. + * Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont + E-cores from Golden Cove P-cores. + * Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15) + Raptor Lake Gracemont E-cores from Raptor Cove P-cores. + * Added (synth) & (uarch synth) decoding for (10,15),(7,8) + Phoenix 2, from Coreboot*. + * Decode Xen tsc mode. + * Added (synth) decoding for (10,15),(6,1,1) Raphael B1. + ------------------------------------------------------------------- Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller -- updaet to 20230120: +- updated to 20230120: * Intel's 13th Generation Core datasheet provides stepping names as well as numbers! So: * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping. @@ -101,7 +217,7 @@ Sat Aug 13 10:39:31 UTC 2022 - Jan Engelhardt - Update to release 20220812 * Corrected (synth) decoding for (0,6),(8,6) Intel Snow - Ridge/Parker Ridge. + Ridge/Parker Ridge. * Added 8000000a/edx X2AVIC flag * Generalized (0,6),(8,14),9,YP stepping case to include Pentium 4425Y, from instlatx64 sample. diff --git a/cpuid.spec b/cpuid.spec index 7f1c28e..e71aaa0 100644 --- a/cpuid.spec +++ b/cpuid.spec @@ -17,7 +17,7 @@ Name: cpuid -Version: 20230120 +Version: 20230406 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later From 529257285bf0218187452c6ac8c40bd7884aa9b31915a8982022c851934e1aa1 Mon Sep 17 00:00:00 2001 From: Jan Engelhardt Date: Fri, 14 Apr 2023 10:37:40 +0000 Subject: [PATCH 2/2] trim changelog to size OBS-URL: https://build.opensuse.org/package/show/utilities/cpuid?expand=0&rev=46 --- cpuid.changes | 130 +++++++++----------------------------------------- 1 file changed, 23 insertions(+), 107 deletions(-) diff --git a/cpuid.changes b/cpuid.changes index 72f36c8..5797eb0 100644 --- a/cpuid.changes +++ b/cpuid.changes @@ -2,117 +2,33 @@ Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich - Update to release 20230406: - * Fixed bug when interpreting leaf 0xb and 0x1f bit widths: - Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1 - in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID - values. - * For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of - level & previous levels" to reflect this definition. - * Support APIC bit fields for the newest 4 topology - layers: module, tile, die, die group. And for the mp version, also - the older cu & pkg levels. - * Use the extended APIC ID's when available in a variety of leaves. + * Support APIC bit fields for the newest 4 topology layers: + module, tile, die, die group. * Support leaf 0xb method for AMD/Hygon. - * Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS. - * Added 7/1/edx AMX-COMPLEX instructions. - * Added 7/2/edx UC-lock disable. - * Added 0x10/n/ecx non-contiguous 1s value supported. - * Added 0x1c/ecx event logging supported bitmap. - * Added 0x23/0/ebx decoding. - * Decode 0x80000026/1/ebx core type & native model. - * For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match - Intel versions in 7/1/eax. - * For 0x80000022/ecx, shorten description, show bitmask only in - hex. + * Added prelim Bergamo A1 stepping from sample. + * Added AMX-COMPLEX instructions, UC-lock disable, + non-contiguous 1s value support, event logging supported + bitmap. * Update CPUID utility with new feature bits as documented in - the AMD Processor Programming Reference for Family 19h and Model 11h: - 0x8000000a/edx extended LVT offset fault change - 0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC, - FsGsKernelGsBaseNonSerializing - 0x80000022/ebx number of available UMC PMCs - 0x80000022/ecx bitmask representing active UMCs - * Differentiate preliminary (uarch synth) for (0,6),(10,10); - (0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores - from their Redwood Cove counterparts. - * Added preliminary (synth) & (uarch synth) for (0,6),(12,6) - Lion Cove & Skymont, from LX*. - * Added 12/0/eax SGX ENCLS EUPDATESVN bit. - * Added 0x1f/*/ecx level type value "die group (6)". - * Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D & - E0 steppings from coreboot*. - * Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen - Xeons to Ice Lake-SP. Also, improved decoding for engr samples where - the brand string omits Xeon & Bronze/Silver/Gold/Platinum. - * Improved (synth) decoding for (0,6),(11,14) Intel N-Series. + the AMD Processor Programming Reference for Family 19h and + Model 11h: extended LVT offset fault cange, enhanced + predictive store forwarding, FSRS, FSRC, + FsGsKernelGsBaseNonSerializing, number of available UMC PMCs, + bitmask representing active UMCs. + * Added (synth) decoding for Sapphire Rapids D & E0 steppings + * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice + Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for + Raptor Lake-H/U/P. * Differentiate (synth) & (uarch synth) for (0,6),(11,14) - Alder Lake-N based on core type, much like for other Alder Lake models. - This corrects the cores to Gracemont. As for Golden Cove, perhaps - P-cores never will exist for this model but, if they do, they should - now be decoded correctly. - * Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P. - * Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P. - * Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made - the following (synth) changes: - * Updated (0,6),(3,7),8 Bay Trail with stepping name C0. - * Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping. - * Corrected (0,6),(4,6),1 Crystal Well to C0 stepping. - * Updated (0,6),(4,7),1 Broadwell to include E0 stepping. - * Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable). - * Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable). - * Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable). - * Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0 - steppings. - * Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable). - * Added (0,6),(6,12),1 Ice Lake B0. - * Updated (0,6),(8,6),4 Snow Ridge with stepping B0. - * Updated (0,6),(8,6),5 Snow Ridge with stepping B1. - * Added (0,6),(8,6),1 Lakefield B2/B3 stepping. - * Corrected (0,6),(8,12),1 Tiger Lake stepping to B1. - * Added (0,6),(8,12),2 Tiger Lake C0. - * Added (0,6),(8,14),10 Coffee Lake D0. - * Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping. - * Added (0,6),(8,15) Sapphire Rapids numerous steppings. - * Updated (0,6),(9,12) Jasper Lake with stepping A1. - * Differentiate (0,6),(8,10) Lakefield P-cores from Tremont - E-cores, much as I previously did for Alder Lake & Raptor Lake. - * For known Hybrid chips (Alder Lake, Raptor Lake & Lakefield), - only decode the uarch if it's one of the two known hybrid types. - However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only), - so also decode core type == 0x00 there. - * In the Intel Core era, uarch families are identified only by - the initial uarch in the family. So the family names in {braces}, - which also are uarch names, can be confusing. So, change (synth) and - (uarch synth) for those families to explain the relationships between - the subsequent uarch and the initial uarch, in the form of - "shrink of", "optim of", and the unusual "backport of". - * Added (4th Gen) to the (synth) description of (10,15),(1,*) - AMD EPYC Genoa. - * Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2 - CPUs to claim 4nm process. - * Corrected 7/1/eax fast REP instructions, where I'd left the - REP prefix out of the description. - * Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and - Event Deliver (FRED). - * Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf - 0x23 is valid. - * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based - on sample from bakerlab.org, which I missed on Oct 3 2022, when I - added the (synth) decoding. - * Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family - 19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and - (7,0) Phoenix, based on their respective PPPR's. - * Added very early (synth) decoding for Lunar Lake. There is - no corresponding (uarch synth) decoding, because no name is yet known - for the uarch. - * Added (0,6),(9,10) Alder Lake Core names: i*-12000. - * Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont - E-cores from Golden Cove P-cores. - * Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15) - Raptor Lake Gracemont E-cores from Raptor Cove P-cores. - * Added (synth) & (uarch synth) decoding for (10,15),(7,8) - Phoenix 2, from Coreboot*. + Alder Lake-N based on core type. + * Differentiate Lakefield P-cores from Tremont E-cores. + * Added (4th Gen) to the (synth) description of AMD EPYC Genoa. + * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0) + * Added PkgType decoding for AMD Family 19h CPUs: Vermeer, + Cezanne/Barcelo, Raphael, and Phoenix, based on their + respective PPPRs. + * Added Alder Lake Core names: i*-12000. * Decode Xen tsc mode. - * Added (synth) decoding for (10,15),(6,1,1) Raphael B1. ------------------------------------------------------------------- Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller