diff --git a/cpuid.changes b/cpuid.changes
index bd5e2b8..c5e9f9c 100644
--- a/cpuid.changes
+++ b/cpuid.changes
@@ -2,61 +2,23 @@
 Wed Jun 21 09:18:20 UTC 2023 - Valentin Lefebvre <valentin.lefebvre@suse.com>
 
 - Update to release 20230614
-  * cpuid.c: Improved (synth) identification for (0,6),(5,5),10 Intel
-    Xeon Scalable (3rd Gen) (Cooper Lake A0), based on 634897 doc.
-  * cpuid.c: Changed (synth) identification for (0,6),(6,12) Intel Xeon
-    D-1700/2700 (Ice Lake-D).  Intel docs 714071 claim the stepping is
-    U1/U2, which contradicts ILPMDF*.  I'm using the actual docs.
-  * cpuid.c: Updated comments with new Intel docs.
-  * cpuid.c: Changed "Intel Scalable" to "Intel Xeon Scalable".
-  * cpuid.man: Added new Intel docs.
-  * cpuid.man: Added 613537, the new pub number for 336065, Intel Xeon
-    Processor Scalable Family Specification Update.
-  * cpuid.c: Added (synth) differentiation for (0,6),(9,10),4 Intel
-    Pentium Gold 8500 series.
-  * cpuid.c: Made the (simple synth) fields non-default.  Too many people
-    were interpreting them as definitive and ignoring the much better
-    (synth) leaf, which uses the entirety of cpuid information.  This
-    impacts leaves 1, 0x80000001, and 0x80860001.  The (simple synth)
-    fields still are available, but only with the -S/--simple option.
-  * cpuid.c: Organized option flags that need to be passed deeply down in
-    the print_reg* functions into a new print_opts_t, which will make
-    future options easier to add.
-  * cpuid.c: Renamed the old "try" variables to "sub".  The word "try" was
-    a remnant of the original leaf 4 subleaf implemntation, before
-    subleaves were commonplace.  For leaf 4, one just kept "trying" to
-    read more cache data until it failed.  But most subleaves don't work
-    that way.  
-  * cpuid.c: Updated (synth) decoding for (0,6),(8,15),{7,8} to mention
-    steppings {S2,S3} from ILPMDF* 20230512.
-  * cpuid.c: Added (synth) decoding for (0,6),(11,14) pure Atom x7000E,
-    as a variation on other Alder Lake-N CPUs.
-  * cpuid.c: Added (synth) decoding for (0,6),(9,10),4 Atom C1100 Arizona
-    Beach.
+  * Improved (synth) identification for Intel Xeon Scalable (3rd
+    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
+    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
+    Arizona Beach.
+  * Made the (simple synth) fields non-default. The (simple synth)
+    fields still are available, but only with the -S/--simple
+    option.
 - Update to release 20230505
-  * cpuid.c: Fixed bug in (multi-processing synth) in the recently
-    rewritten decode_mp_synth().  The CPU counts for higher levels were
-    not dividing out counts from lower levels.  This is analogous to the
-    way print_apic_synth() subtracts out bit widths from lower levels.
-  * cpuid.c: Differentiate Core i3-N300 N-Series from ordinary N-Series.
-    (They appear to differ only in branding.)
-  * cpuid.c: Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
-    space I/O, based on LX* (Michael Kelley PCI pass-thru patches).  Not
-    documented by Microsoft yet.  
-  * cpuid.c: make inability to switch to CPU 0 no longer a fatal error.
-  * cpuid.c: Added (synth) decoding for (0,6),(8,15) Xeon W version of
-    Sapphire Rapids, from instlatx64 sample.
-  * cpuid.c: Corrected (synth) & (uarch synth) for Sapphire Rapids:
-    family is Golden Cove, not Sunny Cove.
-  * cpuid.c: Added (synth) & (uarch synth) Emerald Rapids family:
-    Raptor Cove.
-  * cpuid.c: Added (synth) & (uarch synth) Granite Rapids family:
-    Redwood Cove.
-  * cpuid.c: In decode_uarch_intel, mark Sapphire Rapids, Emerald Rapids
-    & Granite Rapids with core_is_uarch to avoid replicating the name in
-    (synth).
-  * cpuid.c: Added (synth) decoding for (0,6),(10,10),2 Meteor Lake-M B0
-    from Coreboot*. 
+  * Fixed CPU counts for higher levels
+    not dividing out counts from lower levels.
+  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
+  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
+    space I/O, based on LX*.
+  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
+    Meteor Lake-M B0.
+  * Added (synth) & (uarch synth) Emerald Rapids family: Raptor
+    Cove, and Granite Rapids family: Redwood Cove.
 
 -------------------------------------------------------------------
 Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <eich@suse.com>