From b925c54b3a91b26aab0baa9cd8a687c359876125cfd964b3ef37ff0c67b40820 Mon Sep 17 00:00:00 2001 From: vlefebvre Date: Wed, 16 Oct 2024 14:25:06 +0200 Subject: [PATCH] Release to 20240916 Signed-off-by: vlefebvre --- cpuid-20240716.src.tar.gz | 3 --- cpuid-20240916.src.tar.gz | 3 +++ cpuid.changes | 45 +++++++++++++++++++++++++++++++++++++++ cpuid.spec | 2 +- 4 files changed, 49 insertions(+), 4 deletions(-) delete mode 100644 cpuid-20240716.src.tar.gz create mode 100644 cpuid-20240916.src.tar.gz diff --git a/cpuid-20240716.src.tar.gz b/cpuid-20240716.src.tar.gz deleted file mode 100644 index 0a53a6e..0000000 --- a/cpuid-20240716.src.tar.gz +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:6fc4d666a601296fed005ce8277f2c65d1f56d717c4efb6527ad4112c6573ee4 -size 155562 diff --git a/cpuid-20240916.src.tar.gz b/cpuid-20240916.src.tar.gz new file mode 100644 index 0000000..241a894 --- /dev/null +++ b/cpuid-20240916.src.tar.gz @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4fa933b9d571349d8cfff29942769b793d4ce808eb97b594bbbf86d4d017293d +size 157553 diff --git a/cpuid.changes b/cpuid.changes index e1cf9ed..5882af0 100644 --- a/cpuid.changes +++ b/cpuid.changes @@ -1,3 +1,48 @@ +------------------------------------------------------------------- +Wed Oct 16 12:19:15 UTC 2024 - Valentin Lefebvre + +- Update to release 20240916 + * cpuid.c: Updated AMD Zen 3/4/5 die processes with specific TSMC nodes, + where known & consistent. (Earlier generations appear to be a mix of + GloFo & TSMC.) + * cpuid.c: Updated AMD Instinct MI300 CPUs to MI300A/C. + * cpuid.c: Based on LLVM patch from AMD's Ganesh Gopalasubramanian: + * cpuid.c: Added numerous early AMD core names for Zen 5. + * cpuid.c: Updated AMD 4700S Desktop Kit from Oberon, the GPU name, to + Cardinal, the CPU core name. + * cpuid.c: Added AMD 4800S Desktop Kit ProjectX core name. + * cpuid.c: Fixed a warning about a potential buffer overflow in + decode_synth_amd detected by gcc at -O2 (detected via an + interprocedural optimaztion, I think). + * Made new release. + * cpuid.c: For (0,6),(11,14),0 Intel N-Series, add Twin Lake core + name. It can only be distinguished with MSR IA32_PLATFORM_ID (17h) -- + or by brand name (which would be unreliable if new brandings appear). + * cpuid.c: For (synth) decoding of VIA (0,7),(5,11), removed Zhaoxin + KaiXian KX-7000 possibility, based on findings that those likely are + rebadged Intel CPUs instead. + * cpuid.c: In decode_uarch_intel(), for Jintide Gen1, used family field + to indicate that they're based on Intel Skylake. + * cpuid.c: In decode_uarch_via(), for ZhangJiang CPU's, used family + field to to indicate that they're based on VIA C7. Did not provide a + family for WuDaoKou or LuJiaZui, because it isn't clear how far + they have diverged. + * cpuid.c: Changed comments after 743844-012 corrects (0,6),(11,15),5 + to be stepping H0. + * cpuid.c: In decode_uarch_hygon(), widened Moksha name to include + all of Hygon family (9,15). Based on Jinke F. patch to perfmon2, + which applies the name to all of fam18h. + * cpuid.c: In decode_uarch_hygon(), used family field to indicate that + it's based on AMD Zen. + * cpuid.c: Added missing AMD Ryzen numbers: Rembrandt=6000/7000, + Mendocino=7000, Raphael=7000, Phoenix=7000/8000, Granite Ridge=9000. + * cpuid.c: Updated synth decoding for (0,6),(10,15) to detect + Intel Xeon 6 (Sierra Forest) CPUs. + * cpuid.c: For (0,6),(8,15),8, add Xeon Scalable (5th Gen). Some of + these have been rebranded from 4th Gen to 5th Gen: LCC U1. + * cpuid.c: Added 0x80000007/edx fast CPPC, mentioned in the PPR for + Family 19h Model 61h, Revision B1. + ------------------------------------------------------------------- Mon Aug 5 16:05:55 UTC 2024 - Valentin Lefebvre diff --git a/cpuid.spec b/cpuid.spec index b4caac9..553d956 100644 --- a/cpuid.spec +++ b/cpuid.spec @@ -17,7 +17,7 @@ Name: cpuid -Version: 20240716 +Version: 20240916 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later -- 2.45.2