jengelh/cpuid
SHA256
1
0
Fork 1
forked from pool/cpuid
Code Pull Requests Activity
92fdeabf67
cpuid/cpuid.changes
Jan Engelhardt 92fdeabf67 Accepting request 1079377 from home:eeich:branches:utilities 
- Update to release 20230406:
  * Fixed bug when interpreting leaf 0xb and 0x1f bit widths:
    Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1
    in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
    values.
  * For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
    level & previous levels" to reflect this definition.
  * Support APIC bit fields for the newest 4 topology
    layers: module, tile, die, die group.  And for the mp version, also
    the older cu & pkg levels.
  * Use the extended APIC ID's when available in a variety of leaves.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
  * Added 7/1/edx AMX-COMPLEX instructions.
  * Added 7/2/edx UC-lock disable.
  * Added 0x10/n/ecx non-contiguous 1s value supported.
  * Added 0x1c/ecx event logging supported bitmap.
  * Added 0x23/0/ebx decoding.
  * Decode 0x80000026/1/ebx core type & native model.
  * For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
    Intel versions in 7/1/eax.
  * For 0x80000022/ecx, shorten description, show bitmask only in
    hex.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and Model 11h:
    0x8000000a/edx extended LVT offset fault change
    0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing
    0x80000022/ebx number of available UMC PMCs
    0x80000022/ecx bitmask representing active UMCs

OBS-URL: https://build.opensuse.org/request/show/1079377
OBS-URL: https://build.opensuse.org/package/show/utilities/cpuid?expand=0&rev=45
2023-04-14 08:56:36 +00:00

492 lines
22 KiB
Plaintext
Raw Blame History

-------------------------------------------------------------------
Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <eich@suse.com>
- Update to release 20230406:
* Fixed bug when interpreting leaf 0xb and 0x1f bit widths:
Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1
in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
values.
* For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
level & previous levels" to reflect this definition.
* Support APIC bit fields for the newest 4 topology
layers: module, tile, die, die group. And for the mp version, also
the older cu & pkg levels.
* Use the extended APIC ID's when available in a variety of leaves.
* Support leaf 0xb method for AMD/Hygon.
* Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
* Added 7/1/edx AMX-COMPLEX instructions.
* Added 7/2/edx UC-lock disable.
* Added 0x10/n/ecx non-contiguous 1s value supported.
* Added 0x1c/ecx event logging supported bitmap.
* Added 0x23/0/ebx decoding.
* Decode 0x80000026/1/ebx core type & native model.
* For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
Intel versions in 7/1/eax.
* For 0x80000022/ecx, shorten description, show bitmask only in
hex.
* Update CPUID utility with new feature bits as documented in
the AMD Processor Programming Reference for Family 19h and Model 11h:
0x8000000a/edx extended LVT offset fault change
0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
FsGsKernelGsBaseNonSerializing
0x80000022/ebx number of available UMC PMCs
0x80000022/ecx bitmask representing active UMCs
* Differentiate preliminary (uarch synth) for (0,6),(10,10);
(0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores
from their Redwood Cove counterparts.
* Added preliminary (synth) & (uarch synth) for (0,6),(12,6)
Lion Cove & Skymont, from LX*.
* Added 12/0/eax SGX ENCLS EUPDATESVN bit.
* Added 0x1f/*/ecx level type value "die group (6)".
* Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D &
E0 steppings from coreboot*.
* Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen
Xeons to Ice Lake-SP. Also, improved decoding for engr samples where
the brand string omits Xeon & Bronze/Silver/Gold/Platinum.
* Improved (synth) decoding for (0,6),(11,14) Intel N-Series.
* Differentiate (synth) & (uarch synth) for (0,6),(11,14)
Alder Lake-N based on core type, much like for other Alder Lake models.
This corrects the cores to Gracemont. As for Golden Cove, perhaps
P-cores never will exist for this model but, if they do, they should
now be decoded correctly.
* Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P.
* Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P.
* Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made
the following (synth) changes:
* Updated (0,6),(3,7),8 Bay Trail with stepping name C0.
* Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping.
* Corrected (0,6),(4,6),1 Crystal Well to C0 stepping.
* Updated (0,6),(4,7),1 Broadwell to include E0 stepping.
* Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable).
* Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable).
* Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable).
* Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0
steppings.
* Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable).
* Added (0,6),(6,12),1 Ice Lake B0.
* Updated (0,6),(8,6),4 Snow Ridge with stepping B0.
* Updated (0,6),(8,6),5 Snow Ridge with stepping B1.
* Added (0,6),(8,6),1 Lakefield B2/B3 stepping.
* Corrected (0,6),(8,12),1 Tiger Lake stepping to B1.
* Added (0,6),(8,12),2 Tiger Lake C0.
* Added (0,6),(8,14),10 Coffee Lake D0.
* Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping.
* Added (0,6),(8,15) Sapphire Rapids numerous steppings.
* Updated (0,6),(9,12) Jasper Lake with stepping A1.
* Differentiate (0,6),(8,10) Lakefield P-cores from Tremont
E-cores, much as I previously did for Alder Lake & Raptor Lake.
* For known Hybrid chips (Alder Lake, Raptor Lake & Lakefield),
only decode the uarch if it's one of the two known hybrid types.
However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only),
so also decode core type == 0x00 there.
* In the Intel Core era, uarch families are identified only by
the initial uarch in the family. So the family names in {braces},
which also are uarch names, can be confusing. So, change (synth) and
(uarch synth) for those families to explain the relationships between
the subsequent uarch and the initial uarch, in the form of
"shrink of", "optim of", and the unusual "backport of".
* Added (4th Gen) to the (synth) description of (10,15),(1,*)
AMD EPYC Genoa.
* Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2
CPUs to claim 4nm process.
* Corrected 7/1/eax fast REP instructions, where I'd left the
REP prefix out of the description.
* Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and
Event Deliver (FRED).
* Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf
0x23 is valid.
* Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based
on sample from bakerlab.org, which I missed on Oct 3 2022, when I
added the (synth) decoding.
* Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family
19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and
(7,0) Phoenix, based on their respective PPPR's.
* Added very early (synth) decoding for Lunar Lake. There is
no corresponding (uarch synth) decoding, because no name is yet known
for the uarch.
* Added (0,6),(9,10) Alder Lake Core names: i*-12000.
* Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont
E-cores from Golden Cove P-cores.
* Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15)
Raptor Lake Gracemont E-cores from Raptor Cove P-cores.
* Added (synth) & (uarch synth) decoding for (10,15),(7,8)
Phoenix 2, from Coreboot*.
* Decode Xen tsc mode.
* Added (synth) decoding for (10,15),(6,1,1) Raphael B1.
-------------------------------------------------------------------
Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller <dmueller@suse.com>
- updated to 20230120:
* Intel's 13th Generation Core datasheet provides stepping names as
well as numbers! So:
* cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
* cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
steppings, and clarified case for unknown stepping.
* cpuid.man: Added 743844: 13th Generation Core datasheet.
* cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
* cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
* cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
* cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
* cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
* cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
* cpuid.c: Added several 7/2/edx bits.
* cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
* cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
relevant for XCR0.
* cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
hex bitmask.
* cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
* cpuid.c: Renamed 0x1a: Native Model ID.
* cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake
from MSR_CPUID_table*.
* cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
based on instlatx64 sample.
* cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
Emerald Rapids CPUs.
* cpuid.c: Added 7/1/eax LASS: linear address space separation.
* cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
should use minus-one notation.
* cpuid.c: Certain leaves cannot be displayed correctly in isolation,
i.e. without information about other leaves saved in the stash. For
example, the display for leaf 3 uses bits saved from leaf 1. If the
-l/--leaf option is used to restrict cpuid to reading only a single
leaf, such leaves now are displayed as raw hex, rather than with
incorrect information. This is handled by passing a NULL stash to
print_reg() and below, and by many new checks for a NULL stash.
* cpuid.c: Updated cache associativity strings used in 0x80000006 and
0x80000019 leaves to use value ranges, as in AMD docs.
* cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
0x80000020/0 register EBX, not ECX.
* cpuid.c: Added 0x80000026/0/edx extended APIC ID.
* cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from
AMD 57095 revision guide.
* cpuid.man: Added AMD 57095 revision guides, and some older guides that
I'd forgotten.
-------------------------------------------------------------------
Mon Dec 05 09:50:12 UTC 2022 - Valentin Lefebvre <valentin.lefebvre@suse.com>
- Update to release 20221201
* Clarified synth decoding for Intel Xeon D-1700.
* Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
instlatx64 sample.
* Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
* Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
* Added synth & uarch decoding for (10,15),(10,1) Bergamo.
* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
* Added 0x8000001f/eax bits: RMPQUERY instruction support,
VMPL supervisor shadow stack support, VMGEXIT parameter support,
virtual TOM MSR support, IBS virtual support for SEV-ES guests,
SMT protection support, SVSM communication page MSR support,
VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
* Added 0x80000020/0/ecx bit: L3 range reservation support.
* Added 0x80000021/eax bits: automatic IBRS,
CPUID disable for non-privileged.
* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
* Added 0x80000022/ebx field: number of LBR stack entries.
* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
* Added 0x80000026 leaf: AMD Extended CPU Topology.
* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
AMD LBR V2 flag, from LX*.
-------------------------------------------------------------------
Thu Oct 13 14:05:28 UTC 2022 - Valentin Lefebvre <valentin.lefebvre@suse.com>
- Update to release 20221003
* Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
* Added synth & uarch synth decoding for
* (0,6),(11,5) Intel Meteor Lake
* (0,6),(11,6) Intel Grand Ridge (Crestmont)
* (0,6),(11,14) Intel Granite Rapids
* Renamed 7/0/eax enh hardware feedback to just "Thread
Director".
* Added 7/1/eax instructions.
* Added 0x12/0/eax SGX ENCLU EDECCSA flag.
* Added 0x23 Architecture Performance Monitoring Extended leaf
decoding.
* Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
* Added synth decoding for (10,15),(6,1) Raphael
* Fixed title for AMD 0x8000001a leaf: Performance Optimization
identifiers.
-------------------------------------------------------------------
Sat Aug 13 10:39:31 UTC 2022 - Jan Engelhardt <jengelh@inai.de>
- Update to release 20220812
* Corrected (synth) decoding for (0,6),(8,6) Intel Snow
Ridge/Parker Ridge.
* Added 8000000a/edx X2AVIC flag
* Generalized (0,6),(8,14),9,YP stepping case to include
Pentium 4425Y, from instlatx64 sample.
* Added support for hypervisor+3/ecx (Microsoft) flags.
-------------------------------------------------------------------
Thu Feb 24 21:10:05 UTC 2022 - Andreas Stieger <andreas.stieger@gmx.de>
- update to 20220224:
* Support for AMD Rembrandt E1
* Add hypervisor+4/eax (Xen) expanded destination id bit
* Correction for Alder Lake, Rocket Lake decoding
* Multiple detection and decodings updated
-------------------------------------------------------------------
Mon Nov 15 22:04:30 UTC 2021 - Andreas Stieger <andreas.stieger@gmx.de>
- update to 20211114:
* Many updated and added identified CPU models and variants
* Updated hypervisor support
-------------------------------------------------------------------
Thu Oct 8 08:19:24 UTC 2020 - Josef Möllers <josef.moellers@suse.com>
- Update to 20201006:
Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
"Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
as well as some additional decoding of supported features.
[cpuid-20201006.src.tar.gz, jsc#sle-13189]
-------------------------------------------------------------------
Tue Apr 28 18:54:25 UTC 2020 - Andreas Stieger <andreas.stieger@gmx.de>
- update to 20200427:
* Add synth decoding for AMD Steppe Eagle/Crowned Eagle
(Puma 2014 G-Series), based on instlatx64 sample
* Add 7/0/edx SERIALIZE & TSXLDTRK bit descriptions
* Add 0xf/1/eax Counter width & overflow flag
* Add 0x10/3/ecx per-thread MBA controls flag
* Add 0x8000001f fields
* Add AMD 24594 & 40332 docs
* Correct field lengths in 14/0 and 14/1 subleafs so that
columns line up
* Add CC150 (Coffee Lake R0) synth decoding, based on
instlatx64 example
* Add Jasper Lake A0 stepping (from Coreboot*)
* Update 1/ebx "cpu count" to modern terminology: "maximum
addressible IDs for CPUs in pkg" to avoid user confusion
* Update 4/eax CPU & core count terminology in the same way
-------------------------------------------------------------------
Fri Mar 6 08:24:45 UTC 2020 - Jan Engelhardt <jengelh@inai.de>
- Update to release 20200211
* Zhaoxin decoding
* Name enhancements for models from AMD, VIA, Intel, NSC
* Added SEV cpuid bit.
-------------------------------------------------------------------
Fri Jan 17 13:06:18 UTC 2020 - Josef Möllers <josef.moellers@suse.com>
- Upgrade to release 20200116
many changes in Changelog: many new flags added.
Also added support for Cyrix MediaGX, Matisse B0 stepping,
Hygon CPUs.
[cpuid-20200116.src.tar.gz]
-------------------------------------------------------------------
Sat May 19 23:47:56 UTC 2018 - jengelh@inai.de
- Update to new upstream release 20180519
* Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields.
* Added 7/ecx bit 16: 5-level paging.
* Improved 14/0/ecx descriptions.
* Added hypervisor leaf descriptions from Microsoft's
Hypervisor Top Level Functional Specification (Released
Version 5.0b).
* Added CPUID features documented in PPR for AMD Family 17h
Model 01h B1 (54945 Rev 1.14):
* Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated
instruction).
* Added bits to 80000001/ecx (amd).
* Added bits to 80000007/edx, 8000000a/edx, 8000001a/eax,
8000001b/eax.
* Added 80000007/ebx, 80000007/ecx, 80000008/ebx.
* Added tentative 8000001f descriptions.
-------------------------------------------------------------------
Fri Apr 20 06:33:28 UTC 2018 - josef.moellers@suse.com
- Update to new upstream release 20180419
* Added synth decoding for AMD Zen, Pentium Silver (Gemini
Lake), Xeon Scalable (Bronze, Silver, Gold, Platinium)
(Skylake), Core X-Series (Skylake-X), Bay Trail D0, Bay Trail
A0, Xeon E7-4800/8800 (Broadwell-EX B0), Xeon D-1500N
(Broadwell-DE A1), Bay Trail-I (E3800), Avoton C0 stepping.
* Corrected synth decoding for Bay Trail-M C0 steppings.
* Added new Intel 1b leaf from Intel Architecture.
* Added various bit fields.
-------------------------------------------------------------------
Mon Jan 23 09:54:56 UTC 2017 - jengelh@inai.de
- Update to new upstream release 20170122
* Added synth decoding for Intel Knights Landing B0.
* Added new synth decodings for Intel Kaby Lake.
* Fixed synth decodings for AMD Steamroller and Jaguar.
* Added synth decodings for AMD Puma and Excavator.
* For (6,15),(0,2) Piledriver processors, detect FX series and
report it as Vishera instead of Abu Dhabi/Seoul/Delhi.
* Added general microarchitecure names for AMD (e.g.
Piledriver) in addition to specific core names (e.g. Trinity)
for later generation processors. If I have trouble
remembering these, it seems likely other people do too.
* Added synth decoding for Quark X1000.
* Added Intel Atom Z2760 (Clover Trail).
* Added extra synth decodings for some Ivy Bridge and Sandy
Bridge processors.
-------------------------------------------------------------------
Fri Dec 2 08:55:37 UTC 2016 - jengelh@inai.de
- Update to new upstream release 20161201
* Fixed bugs in the subleaf walks for 0x8000001d (AMD cache
information) and 0x40000003 (Xen hypervisor information) because
the code for them was under wholly the wrong loops.
-------------------------------------------------------------------
Tue Nov 15 08:43:11 UTC 2016 - jengelh@inai.de
- Update to new upstream release 20161114
* cpuid.c: Added -l/--leaf and -s/--subleaf options to cause
cpuid to dump just the specified leaf and subleaf. If
-s/--subleaf is not specified, it is assumed to be 0. The
intended purpose for this is to display raw dumps of
not-yet-supported leaves.
* cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and
CLWB decoding to 7/ebx.
* cpuid.c: Added AVX512VBMI to 7/ecx.
* cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring
support.
* cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx.
* cpuid.c: Added 0x15/ecx nominal core crystal clock decoding.
* cpuid.c: In print_17_0_ebx, corrected reversed scheme
encodings.
* cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0
stepping.
* cpuid.c: Added synth decoding comment about Braswell D1
stepping, but its stepping number is not documented.
* cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake
processors.
* cpuid.c: Added synth decoding for Apollo Lake processors.
* cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake
processors.
* cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags.
* cpuid.c: Add Knights Mill (KNM) CPUID.
-------------------------------------------------------------------
Tue Aug 30 08:57:28 UTC 2016 - jengelh@inai.de
- Update to new upstream release 20160814
* cpuinfo2cpuid: Added a script that takes input from a
/proc/cpuinfo file and converts it into suitable input to
cpuid. The information that cpuid is capable of producing based
on this very limited input information is slight, but
apparently there is interest in getting the synthesized (synth)
leaf from this.
* Support SGX, MPX, BNDLDX/BNDSTX, RDPID, and IA32_XSS PT state.
* Add information for Skylake, Broadwell, Broadwell-E and -EX
processors, Atom C2000 (Avoton) with A0/A1 steppings, Atom
Z3n00 (Bay Trail) stepping 1, Xeon D-1500 (Broadwell-DE) V2
stepping, corrected Atom Z8000 (Cherry Trail), added Atom S1200
(Centerton) and VIA Eden.
-------------------------------------------------------------------
Sat Nov 7 11:37:43 UTC 2015 - jengelh@inai.de
- Update to new upstream release 20151017
* Updated synth decoding for Broadwell processors.
* Added 0xd leaf field.
* Updated and expanded 0x14 leaf fields.
* Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX).
* Added synth decoding for Intel Core i5/i7 (Skylake).
* Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d.
* added synth decoding for Knights Landing.
* Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx.
* Renamed 0xf leaves to include "Monitoring".
* Added 0x10 leaves for QoS Enforcement.
* Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3.
* Added missing i7 synth decoding for (0,6),(3,14).
* Corrected Atom Z3000 model & stepping which were bafflingly
wrong: (0,6)(3,5),1 -> (0,6)(3,7),8.
* Corrected other Bay Trail stepping names for Celeron/Pentium
N and J series.
* Added synth decoding for Intel Xeon Phi (Knights Corner).
* Added synth decoding for Intel Atom C2000 (Avoton).
* Added synth decoding for Intel Xeon E5-x600 (Haswell-EP).
* Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP).
* Added synth decoding for Intel Core M (Broadwell-Y).
* Added synth decoding for Intel Xeon D-1500 (Broadwell-DE).
* Added synth decoding for Intel i7-5000 Extreme (Haswell R2).
* Added synth decoding for Intel Atom Z8000 (Cherry Trail).
* Added synth decoding for Intel Pentium/Celeron N3000
-------------------------------------------------------------------
Tue Jun 9 16:25:47 UTC 2015 - jengelh@inai.de
- Update to new upstream release 20150606
* Support for several leaf updates, including information on
XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. Decoding for
more Haswell processors, Broadwell, Cherry Trail, and Avoton.
- %doc is already implicit for manpages
-------------------------------------------------------------------
Mon Aug 12 10:33:26 UTC 2013 - jengelh@inai.de
- Update to new upstream release 20130610
* Add lost Opteron 3200 strings
-------------------------------------------------------------------
Mon Jun 10 14:01:53 UTC 2013 - jengelh@inai.de
- Update to new upstream release 20130609
* support for many new CPU types
- Wrap description at 70 cols; remove redundant %clean section
-------------------------------------------------------------------
Wed Jun 1 22:05:31 UTC 2011 - pascal.bleser@opensuse.org
- update to 20110305
- moved to utilities
-------------------------------------------------------------------
Sat Dec 22 00:00:00 UTC 2007 - guru@unixtech.be
- moved to openSUSE Build Service
-------------------------------------------------------------------
Mon Sep 18 00:00:00 UTC 2006 - guru@unixtech.be
- new upstream version
-------------------------------------------------------------------
Wed Aug 23 00:00:00 UTC 2006 - guru@unixtech.be
- new upstream version
-------------------------------------------------------------------
Tue Aug 8 00:00:00 UTC 2006 - guru@unixtech.be
- new upstream version
-------------------------------------------------------------------
Mon Jul 31 00:00:00 UTC 2006 - guru@unixtech.be
- added binary stripping on SUSE < 9.3
- removed Packager and Distribution, injected by rpmmacros
- new upstream version
-------------------------------------------------------------------
Mon Apr 3 00:00:00 UTC 2006 - guru@unixtech.be
- new package
View Git Blame Copy Permalink