From 999d9ff1ba3389019789653fd5d4597887e7cf9de06192a34e1f65947837ca6d Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Fri, 10 Apr 2020 09:55:34 +0000 Subject: [PATCH 1/2] Accepting request 792829 from home:lwfinger:branches:Virtualization - Change default display type for openSUSE virtual machines. The default type has been VMSVGA; however, this display type fails to utilize driver vboxvideo. thus the display size is fixed. This problem is under investigation, but until a fix is found, the default is changed to VBoxVGA with file "add change_default_display.patch". - Makefile in the kernel-host-source package has a typo bug fixed (boo#1168910) and a large number of warnings are fixed. OBS-URL: https://build.opensuse.org/request/show/792829 OBS-URL: https://build.opensuse.org/package/show/Virtualization/virtualbox?expand=0&rev=545 --- change_default_display.patch | 20 ++ fixes_for_5.5.patch | 668 ++++++++++++++++++++++++++++++++++- fixes_for_gcc10.patch | 35 +- fixes_for_leap15.2.patch | 2 +- vbox-fpie.diff | 8 - virtualbox.changes | 11 + virtualbox.spec | 3 + 7 files changed, 704 insertions(+), 43 deletions(-) create mode 100644 change_default_display.patch diff --git a/change_default_display.patch b/change_default_display.patch new file mode 100644 index 0000000..7ba1bd3 --- /dev/null +++ b/change_default_display.patch @@ -0,0 +1,20 @@ +Index: VirtualBox-6.1.4/src/VBox/Main/src-all/Global.cpp +=================================================================== +--- VirtualBox-6.1.4.orig/src/VBox/Main/src-all/Global.cpp ++++ VirtualBox-6.1.4/src/VBox/Main/src-all/Global.cpp +@@ -284,13 +284,13 @@ const Global::OSType Global::sOSTypes[] + + { "Linux", "Linux", "OpenSUSE", "openSUSE (32-bit)", + VBOXOSTYPE_OpenSUSE, VBOXOSHINT_RTCUTC | VBOXOSHINT_USBTABLET | VBOXOSHINT_X2APIC, +- 1024, 16, 8 * _1G64, GraphicsControllerType_VMSVGA, NetworkAdapterType_I82540EM, 0, StorageControllerType_PIIX4, StorageBus_IDE, ++ 1024, 16, 8 * _1G64, GraphicsControllerType_VBoxVGA, NetworkAdapterType_I82540EM, 0, StorageControllerType_PIIX4, StorageBus_IDE, + StorageControllerType_IntelAhci, StorageBus_SATA, ChipsetType_PIIX3, AudioControllerType_AC97, AudioCodecType_AD1980 }, + + { "Linux", "Linux", "OpenSUSE_64", "openSUSE (64-bit)", + VBOXOSTYPE_OpenSUSE_x64, VBOXOSHINT_64BIT | VBOXOSHINT_HWVIRTEX | VBOXOSHINT_IOAPIC | VBOXOSHINT_RTCUTC + | VBOXOSHINT_USBTABLET | VBOXOSHINT_X2APIC, +- 1024, 16, 8 * _1G64, GraphicsControllerType_VMSVGA, NetworkAdapterType_I82540EM, 0, StorageControllerType_PIIX4, StorageBus_IDE, ++ 1024, 16, 8 * _1G64, GraphicsControllerType_VBoxVGA, NetworkAdapterType_I82540EM, 0, StorageControllerType_PIIX4, StorageBus_IDE, + StorageControllerType_IntelAhci, StorageBus_SATA, ChipsetType_PIIX3, AudioControllerType_AC97, AudioCodecType_AD1980 }, + + { "Linux", "Linux", "Turbolinux", "Turbolinux (32-bit)", diff --git a/fixes_for_5.5.patch b/fixes_for_5.5.patch index 41e40ef..959cd2a 100644 --- a/fixes_for_5.5.patch +++ b/fixes_for_5.5.patch @@ -27,22 +27,30 @@ Index: VirtualBox-6.1.4/src/VBox/HostDrivers/linux/Makefile # We want to build on Linux 2.6.18 and later kernels. ifneq ($(filter-out 1.% 2.0.% 2.1.% 2.2.% 2.3.% 2.4.% 2.5.%,$(KERN_VER)),) -@@ -64,6 +62,7 @@ vboxnetflt: vboxdrv - if [ -f vboxdrv/Module.symvers ]; then \ - cp vboxdrv/Module.symvers vboxnetflt; \ - fi; \ +@@ -61,55 +59,38 @@ vboxdrv: + + vboxnetflt: vboxdrv + @if [ -d vboxnetflt ]; then \ +- if [ -f vboxdrv/Module.symvers ]; then \ +- cp vboxdrv/Module.symvers vboxnetflt; \ +- fi; \ + export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxnetflt/Module.symvers; \ echo "=== Building 'vboxnetflt' module ==="; \ - $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxnetflt/Module.symvers) -C vboxnetflt || exit 1; \ +- $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxnetflt/Module.symvers) -C vboxnetflt || exit 1; \ ++ $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxdrv/Module.symvers) -C vboxnetflt || exit 1; \ cp vboxnetflt/vboxnetflt.ko .; \ -@@ -75,41 +74,29 @@ vboxnetadp: vboxdrv - if [ -f vboxdrv/Module.symvers ]; then \ - cp vboxdrv/Module.symvers vboxnetadp; \ - fi; \ + echo; \ + fi + + vboxnetadp: vboxdrv + @if [ -d vboxnetadp ]; then \ +- if [ -f vboxdrv/Module.symvers ]; then \ +- cp vboxdrv/Module.symvers vboxnetadp; \ +- fi; \ + export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxnetadp/Module.symvers; \ echo "=== Building 'vboxnetadp' module ==="; \ - $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxnetadp/Module.symvers) -C vboxnetadp || exit 1; \ -+ $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxpci/Module.symvers) -C vboxnetadp || exit 1; \ ++ $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxdrv/Module.symvers) -C vboxnetadp || exit 1; \ cp vboxnetadp/vboxnetadp.ko .; \ echo; \ fi @@ -81,7 +89,7 @@ Index: VirtualBox-6.1.4/src/VBox/HostDrivers/linux/Makefile install: endif -@@ -122,16 +109,13 @@ clean: +@@ -122,16 +103,13 @@ clean: @if [ -d vboxnetadp ]; then \ $(MAKE) -C vboxnetadp clean; \ fi @@ -100,7 +108,7 @@ Index: VirtualBox-6.1.4/src/VBox/HostDrivers/linux/Makefile if grep "^$$module " /proc/modules >/dev/null; then \ echo "Removing previously installed $$module module"; \ /sbin/rmmod $$module; \ -@@ -139,7 +123,7 @@ unload: +@@ -139,7 +117,7 @@ unload: done load: unload @@ -149,3 +157,639 @@ Index: VirtualBox-6.1.4/src/VBox/Additions/linux/Makefile $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxvideo install; \ fi +Index: VirtualBox-6.1.4/include/iprt/x86.h +=================================================================== +--- VirtualBox-6.1.4.orig/include/iprt/x86.h ++++ VirtualBox-6.1.4/include/iprt/x86.h +@@ -840,37 +840,59 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI + * reserved flags. + * @{ */ + /** Bit 0 - PE - Protection Enabled */ ++#ifndef X86_CR0_PE + #define X86_CR0_PE RT_BIT_32(0) ++#endif + #define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0) + /** Bit 1 - MP - Monitor Coprocessor */ ++#ifndef X86_CR0_MP + #define X86_CR0_MP RT_BIT_32(1) ++#endif + #define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1) + /** Bit 2 - EM - Emulation. */ ++#ifndef X86_CR0_EM + #define X86_CR0_EM RT_BIT_32(2) ++#endif + #define X86_CR0_EMULATE_FPU RT_BIT_32(2) + /** Bit 3 - TS - Task Switch. */ ++#ifndef X86_CR0_TS + #define X86_CR0_TS RT_BIT_32(3) ++#endif + #define X86_CR0_TASK_SWITCH RT_BIT_32(3) + /** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */ ++#ifndef X86_CR0_ET + #define X86_CR0_ET RT_BIT_32(4) ++#endif + #define X86_CR0_EXTENSION_TYPE RT_BIT_32(4) + /** Bit 5 - NE - Numeric error (486+). */ ++#ifndef X86_CR0_NE + #define X86_CR0_NE RT_BIT_32(5) ++#endif + #define X86_CR0_NUMERIC_ERROR RT_BIT_32(5) + /** Bit 16 - WP - Write Protect (486+). */ ++#ifndef X86_CR0_WP + #define X86_CR0_WP RT_BIT_32(16) ++#endif + #define X86_CR0_WRITE_PROTECT RT_BIT_32(16) + /** Bit 18 - AM - Alignment Mask (486+). */ ++#ifndef X86_CR0_AM + #define X86_CR0_AM RT_BIT_32(18) ++#endif + #define X86_CR0_ALIGMENT_MASK RT_BIT_32(18) + /** Bit 29 - NW - Not Write-though (486+). */ ++#ifndef X86_CR0_NW + #define X86_CR0_NW RT_BIT_32(29) ++#endif + #define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29) + /** Bit 30 - WP - Cache Disable (486+). */ ++#ifndef X86_CR0_CD + #define X86_CR0_CD RT_BIT_32(30) ++#endif + #define X86_CR0_CACHE_DISABLE RT_BIT_32(30) + /** Bit 31 - PG - Paging. */ ++#ifndef X86_CR0_PG + #define X86_CR0_PG RT_BIT_32(31) ++#endif + #define X86_CR0_PAGING RT_BIT_32(31) + #define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */ + /** @} */ +@@ -879,9 +901,13 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI + /** @name CR3 + * @{ */ + /** Bit 3 - PWT - Page-level Writes Transparent. */ ++#ifndef X86_CR3_PWT + #define X86_CR3_PWT RT_BIT_32(3) ++#endif + /** Bit 4 - PCD - Page-level Cache Disable. */ ++#ifndef X86_CR3_PCD + #define X86_CR3_PCD RT_BIT_32(4) ++#endif + /** Bits 12-31 - - Page directory page number. */ + #define X86_CR3_PAGE_MASK (0xfffff000) + /** Bits 5-31 - - PAE Page directory page number. */ +@@ -894,46 +920,84 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI + /** @name CR4 + * @{ */ + /** Bit 0 - VME - Virtual-8086 Mode Extensions. */ ++#ifndef X86_CR4_VME + #define X86_CR4_VME RT_BIT_32(0) ++#endif + /** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */ ++#ifndef X86_CR4_PVI + #define X86_CR4_PVI RT_BIT_32(1) ++#endif + /** Bit 2 - TSD - Time Stamp Disable. */ ++#ifndef X86_CR4_TSD + #define X86_CR4_TSD RT_BIT_32(2) ++#endif + /** Bit 3 - DE - Debugging Extensions. */ ++#ifndef X86_CR4_DE + #define X86_CR4_DE RT_BIT_32(3) ++#endif + /** Bit 4 - PSE - Page Size Extension. */ ++#ifndef X86_CR4_PSE + #define X86_CR4_PSE RT_BIT_32(4) ++#endif + /** Bit 5 - PAE - Physical Address Extension. */ ++#ifndef X86_CR4_PAE + #define X86_CR4_PAE RT_BIT_32(5) ++#endif + /** Bit 6 - MCE - Machine-Check Enable. */ ++#ifndef X86_CR4_MCE + #define X86_CR4_MCE RT_BIT_32(6) ++#endif + /** Bit 7 - PGE - Page Global Enable. */ ++#ifndef X86_CR4_PGE + #define X86_CR4_PGE RT_BIT_32(7) ++#endif + /** Bit 8 - PCE - Performance-Monitoring Counter Enable. */ ++#ifndef X86_CR4_PCE + #define X86_CR4_PCE RT_BIT_32(8) ++#endif + /** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */ ++#ifndef X86_CR4_OSFXSR + #define X86_CR4_OSFXSR RT_BIT_32(9) ++#endif + /** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */ + #define X86_CR4_OSXMMEEXCPT RT_BIT_32(10) + /** Bit 11 - UMIP - User-Mode Instruction Prevention. */ ++#ifndef X86_CR4_UMIP + #define X86_CR4_UMIP RT_BIT_32(11) ++#endif + /** Bit 13 - VMXE - VMX mode is enabled. */ ++#ifndef X86_CR4_VMXE + #define X86_CR4_VMXE RT_BIT_32(13) ++#endif + /** Bit 14 - SMXE - Safer Mode Extensions Enabled. */ ++#ifndef X86_CR4_SMXE + #define X86_CR4_SMXE RT_BIT_32(14) ++#endif + /** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */ ++#ifndef X86_CR4_FSGSBASE + #define X86_CR4_FSGSBASE RT_BIT_32(16) ++#endif + /** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */ ++#ifndef X86_CR4_PCIDE + #define X86_CR4_PCIDE RT_BIT_32(17) ++#endif + /** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor + * extended states. */ ++#ifndef X86_CR4_OSXSAVE + #define X86_CR4_OSXSAVE RT_BIT_32(18) ++#endif + /** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */ ++#ifndef X86_CR4_SMEP + #define X86_CR4_SMEP RT_BIT_32(20) ++#endif + /** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */ ++#ifndef X86_CR4_SMAP + #define X86_CR4_SMAP RT_BIT_32(21) ++#endif + /** Bit 22 - PKE - Protection Key Enable. */ ++#ifndef X86_CR4_PKE + #define X86_CR4_PKE RT_BIT_32(22) ++#endif + /** Bit 23 - CET - Control-flow Enhancement Technology enabled. */ + #define X86_CR4_CET RT_BIT_32(23) + /** @} */ +@@ -1147,12 +1211,16 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + /** Machine check type register (P5). */ + #define MSR_P5_MC_TYPE UINT32_C(0x00000001) + /** Time Stamp Counter. */ ++#ifndef MSR_IA32_TSC + #define MSR_IA32_TSC 0x10 ++#endif + #define MSR_IA32_CESR UINT32_C(0x00000011) + #define MSR_IA32_CTR0 UINT32_C(0x00000012) + #define MSR_IA32_CTR1 UINT32_C(0x00000013) + ++#ifndef MSR_IA32_PLATFORM_ID + #define MSR_IA32_PLATFORM_ID 0x17 ++#endif + + #ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */ + # define MSR_IA32_APICBASE 0x1b +@@ -1178,7 +1246,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_CORE_THREAD_COUNT 0x35 + + /** CPU Feature control. */ ++#ifndef MSR_IA32_FEATURE_CONTROL + #define MSR_IA32_FEATURE_CONTROL 0x3A ++#endif + /** Feature control - Lock MSR from writes (R/W0). */ + #define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0) + /** Feature control - Enable VMX inside SMX operation (R/WL). */ +@@ -1203,11 +1273,15 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20) + + /** Per-processor TSC adjust MSR. */ ++#ifndef MSR_IA32_TSC_ADJUST + #define MSR_IA32_TSC_ADJUST 0x3B ++#endif + + /** Spectre control register. + * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */ ++#ifndef MSR_IA32_SPEC_CTRL + #define MSR_IA32_SPEC_CTRL 0x48 ++#endif + /** IBRS - Indirect branch restricted speculation. */ + #define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0) + /** STIBP - Single thread indirect branch predictors. */ +@@ -1215,7 +1289,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + + /** Prediction command register. + * Write only, logical processor scope, no state since write only. */ ++#ifndef MSR_IA32_PRED_CMD + #define MSR_IA32_PRED_CMD 0x49 ++#endif + /** IBPB - Indirect branch prediction barrie when written as 1. */ + #define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0) + +@@ -1226,7 +1302,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_IA32_BIOS_SIGN_ID 0x8B + + /** SMM monitor control. */ ++#ifndef MSR_IA32_SMM_MONITOR_CTL + #define MSR_IA32_SMM_MONITOR_CTL 0x9B ++#endif + /** SMM control - Valid. */ + #define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0) + /** SMM control - VMXOFF unblocks SMI. */ +@@ -1235,10 +1313,14 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff)) + + /** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */ ++#ifndef MSR_IA32_SMBASE + #define MSR_IA32_SMBASE 0x9E ++#endif + + /** General performance counter no. 0. */ ++#ifndef MSR_IA32_PMC0 + #define MSR_IA32_PMC0 0xC1 ++#endif + /** General performance counter no. 1. */ + #define MSR_IA32_PMC1 0xC2 + /** General performance counter no. 2. */ +@@ -1261,18 +1343,26 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_IA32_FSB_CLOCK_STS 0xCD + + /** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */ ++#ifndef MSR_PKG_CST_CONFIG_CONTROL + #define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2) ++#endif + + /** C0 Maximum Frequency Clock Count */ ++#ifndef MSR_IA32_MPERF + #define MSR_IA32_MPERF 0xE7 ++#endif + /** C0 Actual Frequency Clock Count */ ++#ifndef MSR_IA32_APERF + #define MSR_IA32_APERF 0xE8 ++#endif + + /** MTRR Capabilities. */ + #define MSR_IA32_MTRR_CAP 0xFE + + /** Architecture capabilities (bugfixes). */ ++#ifndef MSR_IA32_ARCH_CAPABILITIES + #define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a) ++#endif + /** CPU is no subject to meltdown problems. */ + #define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0) + /** CPU has better IBRS and you can leave it on all the time. */ +@@ -1286,7 +1376,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4) + + /** Flush command register. */ ++#ifndef MSR_IA32_FLUSH_CMD + #define MSR_IA32_FLUSH_CMD UINT32_C(0x10b) ++#endif + /** Flush the level 1 data cache when this bit is written. */ + #define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0) + +@@ -1307,14 +1399,20 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #endif + + /** Machine Check Global Capabilities Register. */ ++#ifndef MSR_IA32_MCG_CAP + #define MSR_IA32_MCG_CAP 0x179 ++#endif + /** Machine Check Global Status Register. */ ++#ifndef MSR_IA32_MCG_STATUS + #define MSR_IA32_MCG_STATUS 0x17A ++#endif + /** Machine Check Global Control Register. */ + #define MSR_IA32_MCG_CTRL 0x17B + + /** Page Attribute Table. */ ++#ifndef MSR_IA32_CR_PAT + #define MSR_IA32_CR_PAT 0x277 ++#endif + /** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4 + * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */ + #define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406) +@@ -1333,36 +1431,58 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_FLEX_RATIO 0x194 + /** Performance state value and starting with Intel core more. + * Apple uses the >=core features to determine TSC granularity on older CPUs. */ ++#ifndef MSR_IA32_PERF_STATUS + #define MSR_IA32_PERF_STATUS 0x198 ++#endif ++#ifndef MSR_IA32_PERF_CTL + #define MSR_IA32_PERF_CTL 0x199 ++#endif ++#ifndef MSR_IA32_THERM_STATUS + #define MSR_IA32_THERM_STATUS 0x19c ++#endif + + /** Offcore response event select registers. */ ++#ifndef MSR_OFFCORE_RSP_0 + #define MSR_OFFCORE_RSP_0 0x1a6 ++#endif ++#ifndef MSR_OFFCORE_RSP_1 + #define MSR_OFFCORE_RSP_1 0x1a7 ++#endif + + /** Enable misc. processor features (R/W). */ ++#ifndef MSR_IA32_MISC_ENABLE + #define MSR_IA32_MISC_ENABLE 0x1A0 ++#endif + /** Enable fast-strings feature (for REP MOVS and REP STORS). */ + #define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0) + /** Automatic Thermal Control Circuit Enable (R/W). */ ++#ifndef MSR_IA32_MISC_ENABLE_TCC + #define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3) ++#endif + /** Performance Monitoring Available (R). */ + #define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7) + /** Branch Trace Storage Unavailable (R/O). */ ++#ifndef MSR_IA32_MISC_ENABLE_BTS_UNAVAIL + #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11) ++#endif + /** Precise Event Based Sampling (PEBS) Unavailable (R/O). */ ++#ifndef MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL + #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12) ++#endif + /** Enhanced Intel SpeedStep Technology Enable (R/W). */ + #define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16) + /** If MONITOR/MWAIT is supported (R/W). */ + #define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18) + /** Limit CPUID Maxval to 3 leafs (R/W). */ ++#ifndef MSR_IA32_MISC_ENABLE_LIMIT_CPUID + #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22) ++#endif + /** When set to 1, xTPR messages are disabled (R/W). */ + #define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23) + /** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */ ++#ifndef MSR_IA32_MISC_ENABLE_XD_DISABLE + #define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34) ++#endif + + /** Trace/Profile Resource Control (R/W) */ + #define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9) +@@ -1500,7 +1620,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + /** @} */ + + /** Intel TSX (Transactional Synchronization Extensions) control MSR. */ ++#ifndef MSR_IA32_TSX_CTRL + #define MSR_IA32_TSX_CTRL 0x122 ++#endif + + /** Variable range MTRRs. + * @{ */ +@@ -1550,89 +1672,167 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390 + + /** Precise Event Based sampling (Intel only). */ ++#ifndef MSR_IA32_PEBS_ENABLE + #define MSR_IA32_PEBS_ENABLE 0x3F1 ++#endif + ++#ifndef MSR_DRAM_POWER_LIMIT + #define MSR_IA32_MC0_CTL 0x400 ++#endif ++#ifndef MSR_IA32_MC0_STATUS + #define MSR_IA32_MC0_STATUS 0x401 ++#endif + + /** Basic VMX information. */ ++#ifndef MSR_IA32_VMX_BASIC + #define MSR_IA32_VMX_BASIC 0x480 ++#endif + /** Allowed settings for pin-based VM execution controls. */ ++#ifndef MSR_IA32_VMX_PINBASED_CTLS + #define MSR_IA32_VMX_PINBASED_CTLS 0x481 ++#endif + /** Allowed settings for proc-based VM execution controls. */ ++#ifndef MSR_IA32_VMX_PROCBASED_CTLS + #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 ++#endif + /** Allowed settings for the VM-exit controls. */ ++#ifndef MSR_IA32_VMX_EXIT_CTLS + #define MSR_IA32_VMX_EXIT_CTLS 0x483 ++#endif + /** Allowed settings for the VM-entry controls. */ ++#ifndef MSR_IA32_VMX_ENTRY_CTLS + #define MSR_IA32_VMX_ENTRY_CTLS 0x484 ++#endif + /** Misc VMX info. */ ++#ifndef MSR_IA32_VMX_MISC + #define MSR_IA32_VMX_MISC 0x485 ++#endif + /** Fixed cleared bits in CR0. */ ++#ifndef MSR_IA32_VMX_CR0_FIXED0 + #define MSR_IA32_VMX_CR0_FIXED0 0x486 ++#endif + /** Fixed set bits in CR0. */ ++#ifndef MSR_IA32_VMX_CR0_FIXED1 + #define MSR_IA32_VMX_CR0_FIXED1 0x487 ++#endif + /** Fixed cleared bits in CR4. */ ++#ifndef MSR_IA32_VMX_CR4_FIXED0 + #define MSR_IA32_VMX_CR4_FIXED0 0x488 ++#endif + /** Fixed set bits in CR4. */ ++#ifndef MSR_IA32_VMX_CR4_FIXED1 + #define MSR_IA32_VMX_CR4_FIXED1 0x489 ++#endif + /** Information for enumerating fields in the VMCS. */ ++#ifndef MSR_IA32_VMX_VMCS_ENUM + #define MSR_IA32_VMX_VMCS_ENUM 0x48A ++#endif + /** Allowed settings for secondary proc-based VM execution controls */ ++#ifndef MSR_IA32_VMX_PROCBASED_CTLS2 + #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B ++#endif + /** EPT capabilities. */ ++#ifndef MSR_IA32_VMX_EPT_VPID_CAP + #define MSR_IA32_VMX_EPT_VPID_CAP 0x48C ++#endif + /** Allowed settings of all pin-based VM execution controls. */ ++#ifndef MSR_IA32_VMX_TRUE_PINBASED_CTLS + #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D ++#endif + /** Allowed settings of all proc-based VM execution controls. */ ++#ifndef MSR_IA32_VMX_TRUE_PROCBASED_CTLS + #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E ++#endif + /** Allowed settings of all VMX exit controls. */ ++#ifndef MSR_IA32_VMX_TRUE_EXIT_CTLS + #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F ++#endif + /** Allowed settings of all VMX entry controls. */ ++#ifndef MSR_IA32_VMX_TRUE_ENTRY_CTLS + #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 ++#endif + /** Allowed settings for the VM-function controls. */ ++#ifndef MSR_IA32_VMX_VMFUNC + #define MSR_IA32_VMX_VMFUNC 0x491 ++#endif + + /** Intel PT - Enable and control for trace packet generation. */ ++#ifndef MSR_IA32_RTIT_CTL + #define MSR_IA32_RTIT_CTL 0x570 ++#endif + + /** DS Save Area (R/W). */ ++#ifndef MSR_IA32_DS_AREA + #define MSR_IA32_DS_AREA 0x600 ++#endif + /** Running Average Power Limit (RAPL) power units. */ ++#ifndef MSR_RAPL_POWER_UNIT + #define MSR_RAPL_POWER_UNIT 0x606 ++#endif + /** Package C3 Interrupt Response Limit. */ ++#ifndef MSR_PKGC3_IRTL + #define MSR_PKGC3_IRTL 0x60a ++#endif + /** Package C6/C7S Interrupt Response Limit 1. */ + #define MSR_PKGC_IRTL1 0x60b + /** Package C6/C7S Interrupt Response Limit 2. */ + #define MSR_PKGC_IRTL2 0x60c + /** Package C2 Residency Counter. */ ++#ifndef MSR_PKG_C2_RESIDENCY + #define MSR_PKG_C2_RESIDENCY 0x60d ++#endif + /** PKG RAPL Power Limit Control. */ ++#ifndef MSR_PKG_POWER_LIMIT + #define MSR_PKG_POWER_LIMIT 0x610 ++#endif + /** PKG Energy Status. */ ++#ifndef MSR_PKG_ENERGY_STATUS + #define MSR_PKG_ENERGY_STATUS 0x611 ++#endif + /** PKG Perf Status. */ ++#ifndef MSR_PKG_PERF_STATUS + #define MSR_PKG_PERF_STATUS 0x613 ++#endif + /** PKG RAPL Parameters. */ ++#ifndef MSR_PKG_POWER_INFO + #define MSR_PKG_POWER_INFO 0x614 ++#endif + /** DRAM RAPL Power Limit Control. */ ++#ifndef MSR_DRAM_POWER_LIMIT + #define MSR_DRAM_POWER_LIMIT 0x618 ++#endif + /** DRAM Energy Status. */ ++#ifndef MSR_DRAM_ENERGY_STATUS + #define MSR_DRAM_ENERGY_STATUS 0x619 ++#endif + /** DRAM Performance Throttling Status. */ ++#ifndef MSR_DRAM_PERF_STATUS + #define MSR_DRAM_PERF_STATUS 0x61b ++#endif + /** DRAM RAPL Parameters. */ ++#ifndef MSR_DRAM_POWER_INFO + #define MSR_DRAM_POWER_INFO 0x61c ++#endif + /** Package C10 Residency Counter. */ ++#ifndef MSR_PKG_C10_RESIDENCY + #define MSR_PKG_C10_RESIDENCY 0x632 ++#endif + /** PP0 Energy Status. */ ++#ifndef MSR_PP0_ENERGY_STATUS + #define MSR_PP0_ENERGY_STATUS 0x639 ++#endif + /** PP1 Energy Status. */ ++#ifndef MSR_PP1_ENERGY_STATUS + #define MSR_PP1_ENERGY_STATUS 0x641 ++#endif + /** Turbo Activation Ratio. */ ++#ifndef MSR_TURBO_ACTIVATION_RATIO + #define MSR_TURBO_ACTIVATION_RATIO 0x64c ++#endif + /** Core Performance Limit Reasons. */ ++#ifndef MSR_CORE_PERF_LIMIT_REASONS + #define MSR_CORE_PERF_LIMIT_REASONS 0x64f ++#endif + + /** X2APIC MSR range start. */ + #define MSR_IA32_X2APIC_START 0x800 +@@ -1767,23 +1967,47 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + /** The mask which give the SYSCALL EIP. */ + #define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff) + /** K6 WHCR - Write Handling Control Register. */ ++#ifndef MSR_K6_WHCR + #define MSR_K6_WHCR UINT32_C(0xc0000082) ++#endif + /** K6 UWCCR - UC/WC Cacheability Control Register. */ ++#ifndef MSR_K6_UWCCR + #define MSR_K6_UWCCR UINT32_C(0xc0000085) ++#endif + /** K6 PSOR - Processor State Observability Register. */ ++#ifndef MSR_K6_PSOR + #define MSR_K6_PSOR UINT32_C(0xc0000087) ++#endif + /** K6 PFIR - Page Flush/Invalidate Register. */ ++#ifndef MSR_K6_PFIR + #define MSR_K6_PFIR UINT32_C(0xc0000088) ++#endif + + /** Performance counter MSRs. (AMD only) */ ++#ifndef MSR_K7_EVNTSEL0 + #define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000) ++#endif ++#ifndef MSR_K7_EVNTSEL1 + #define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001) ++#endif ++#ifndef MSR_K7_EVNTSEL2 + #define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002) ++#endif ++#ifndef MSR_K7_EVNTSEL3 + #define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003) ++#endif ++#ifndef MSR_K7_PERFCTR0 + #define MSR_K7_PERFCTR0 UINT32_C(0xc0010004) ++#endif ++#ifndef MSR_K7_PERFCTR1 + #define MSR_K7_PERFCTR1 UINT32_C(0xc0010005) ++#endif ++#ifndef MSR_K7_PERFCTR2 + #define MSR_K7_PERFCTR2 UINT32_C(0xc0010006) ++#endif ++#ifndef MSR_K7_PERFCTR3 + #define MSR_K7_PERFCTR3 UINT32_C(0xc0010007) ++#endif + + /** K8 LSTAR - Long mode SYSCALL target (RIP). */ + #define MSR_K8_LSTAR UINT32_C(0xc0000082) +@@ -1799,14 +2023,20 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C + #define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102) + /** K8 TSC_AUX - Used with RDTSCP. */ + #define MSR_K8_TSC_AUX UINT32_C(0xc0000103) ++#ifndef MSR_K8_SYSCFG + #define MSR_K8_SYSCFG UINT32_C(0xc0010010) ++#endif + #define MSR_K8_HWCR UINT32_C(0xc0010015) + #define MSR_K8_IORRBASE0 UINT32_C(0xc0010016) + #define MSR_K8_IORRMASK0 UINT32_C(0xc0010017) + #define MSR_K8_IORRBASE1 UINT32_C(0xc0010018) + #define MSR_K8_IORRMASK1 UINT32_C(0xc0010019) ++#ifndef MSR_K8_TOP_MEM1 + #define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a) ++#endif ++#ifndef MSR_K8_TOP_MEM2 + #define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d) ++#endif + /** North bridge config? See BIOS & Kernel dev guides for + * details. */ + #define MSR_K8_NB_CFG UINT32_C(0xc001001f) +Index: VirtualBox-6.1.4/include/VBox/vmm/hm_vmx.h +=================================================================== +--- VirtualBox-6.1.4.orig/include/VBox/vmm/hm_vmx.h ++++ VirtualBox-6.1.4/include/VBox/vmm/hm_vmx.h +@@ -1473,7 +1473,9 @@ AssertCompileSize(VMXABORT, 4); + /** VMCS (and related regions) memory type - Uncacheable. */ + #define VMX_BASIC_MEM_TYPE_UC 0 + /** VMCS (and related regions) memory type - Write back. */ ++#ifndef VMX_BASIC_MEM_TYPE_WB + #define VMX_BASIC_MEM_TYPE_WB 6 ++#endif + /** Width of physical addresses used for VMCS and associated memory regions + * (1=32-bit, 0=processor's physical address width). */ + #define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48) +Index: VirtualBox-6.1.4/src/VBox/Additions/linux/drm/vbox_drv.h +=================================================================== +--- VirtualBox-6.1.4.orig/src/VBox/Additions/linux/drm/vbox_drv.h ++++ VirtualBox-6.1.4/src/VBox/Additions/linux/drm/vbox_drv.h +@@ -83,10 +83,8 @@ + # endif + #endif + +-#if defined(CONFIG_SUSE_VERSION) +-# if CONFIG_SUSE_VERSION == 15 && CONFIG_SUSE_PATCHLEVEL == 1 +-# define OPENSUSE_151 +-# endif ++#if defined(CONFIG_SUSE_VERSION) && CONFIG_SUSE_VERSION == 15 && CONFIG_SUSE_PATCHLEVEL == 1 ++# define OPENSUSE_151 + #endif + + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0) || defined(RHEL_71) diff --git a/fixes_for_gcc10.patch b/fixes_for_gcc10.patch index 3431229..2eb4158 100644 --- a/fixes_for_gcc10.patch +++ b/fixes_for_gcc10.patch @@ -19,27 +19,18 @@ Index: VirtualBox-6.1.4/Config.kmk + $(SED_EXT) 's|\([0-9]\)\.\{0,1\}\([0-9]\{0,1\}\)\.\{0,1\}\([0-9]\{0,1\}\).*|$$(int-add $$(int-mul 10000, \1), $$(int-mul 100, $$(firstword \2 0)), $$(firstword \3 0))|' ) + endif endif + # YASM macros - ifndef DONT_USE_YASM -Index: VirtualBox-6.1.4/include/iprt/formats/mach-o.h +Index: VirtualBox-6.1.4/src/VBox/Debugger/DBGCDumpImage.cpp =================================================================== ---- VirtualBox-6.1.4.orig/include/iprt/formats/mach-o.h -+++ VirtualBox-6.1.4/include/iprt/formats/mach-o.h -@@ -38,7 +38,7 @@ - /* cputype */ - #define CPU_ARCH_MASK INT32_C(0xff000000) - #define CPU_ARCH_ABI64 INT32_C(0x01000000) --#define CPU_TYPE_ANY INT32_C(-1) -+#define CPU_TYPE_ANY INT32_C(999) - #define CPU_TYPE_VAX INT32_C(1) - #define CPU_TYPE_MC680x0 INT32_C(6) - #define CPU_TYPE_X86 INT32_C(7) -@@ -53,7 +53,7 @@ - #define CPU_TYPE_POWERPC64 (CPU_TYPE_POWERPC | CPU_ARCH_ABI64) - - /* cpusubtype */ --#define CPU_SUBTYPE_MULTIPLE INT32_C(-1) -+#define CPU_SUBTYPE_MULTIPLE -1 - #define CPU_SUBTYPE_LITTLE_ENDIAN INT32_C(0) - #define CPU_SUBTYPE_BIG_ENDIAN INT32_C(1) - +--- VirtualBox-6.1.4.orig/src/VBox/Debugger/DBGCDumpImage.cpp ++++ VirtualBox-6.1.4/src/VBox/Debugger/DBGCDumpImage.cpp +@@ -468,7 +468,7 @@ static const char *dbgcMachoCpuType(uint + { + switch (uType) + { +- case CPU_TYPE_ANY: return "CPU_TYPE_ANY"; ++ default: return "CPU_TYPE_ANY"; + case CPU_TYPE_VAX: return "VAX"; + case CPU_TYPE_MC680x0: return "MC680x0"; + case CPU_TYPE_X86: return "X86"; diff --git a/fixes_for_leap15.2.patch b/fixes_for_leap15.2.patch index cd6fe2d..1f7ec2e 100644 --- a/fixes_for_leap15.2.patch +++ b/fixes_for_leap15.2.patch @@ -6,7 +6,7 @@ Index: VirtualBox-6.1.0_RC1/src/VBox/HostDrivers/VBoxNetFlt/linux/VBoxNetFlt-lin #define VBOXNETFLT_OS_SPECFIC 1 #include "../VBoxNetFltInternal.h" -+# if CONFIG_SUSE_VERSION == 15 && CONFIG_SUSE_PATCHLEVEL == 2 ++# if defined(CONFIG_SUSE_VERSION) & CONFIG_SUSE_VERSION == 15 && CONFIG_SUSE_PATCHLEVEL == 2 +# define OPENSUSE_152 +# endif + diff --git a/vbox-fpie.diff b/vbox-fpie.diff index 4b6ec49..7970ebd 100644 --- a/vbox-fpie.diff +++ b/vbox-fpie.diff @@ -2,14 +2,6 @@ Index: VirtualBox-6.1.4/Config.kmk =================================================================== --- VirtualBox-6.1.4.orig/Config.kmk +++ VirtualBox-6.1.4/Config.kmk -@@ -2687,7 +2687,6 @@ else - VBOX_GCC_VERSION = $(shell ($(1) -dumpfullversion 2>/dev/null || $(1) -dumpversion) | \ - $(SED_EXT) 's|\([0-9]\)\.\{0,1\}\([0-9]\{0,1\}\)\.\{0,1\}\([0-9]\{0,1\}\).*|$$(int-add $$(int-mul 10000, \1), $$(int-mul 100, $$(firstword \2 0)), $$(firstword \3 0))|' ) - endif -- - # YASM macros - ifndef DONT_USE_YASM - include $(KBUILD_PATH)/tools/YASM.kmk @@ -5533,6 +5532,9 @@ TEMPLATE_VBOXR3HARDENEDEXE_LDFLAGS.darwi ifeq ($(KBUILD_TARGET),linux) # not necessary except USE_LIB_PCAP is defined in SUPR3HardenedMain.cpp diff --git a/virtualbox.changes b/virtualbox.changes index 34471cf..2ce8b1d 100644 --- a/virtualbox.changes +++ b/virtualbox.changes @@ -1,3 +1,14 @@ +------------------------------------------------------------------- +Thu Apr 9 21:49:36 UTC 2020 - Larry Finger + +- Change default display type for openSUSE virtual machines. The default type + has been VMSVGA; however, this display type fails to utilize driver vboxvideo. + thus the display size is fixed. This problem is under investigation, but + until a fix is found, the default is changed to VBoxVGA with file + "add change_default_display.patch". +- Makefile in the kernel-host-source package has a typo bug fixed (boo#1168910) + and a large number of warnings are fixed. + ------------------------------------------------------------------- Sun Mar 29 19:20:48 UTC 2020 - Larry Finger diff --git a/virtualbox.spec b/virtualbox.spec index 7a9d142..7c9e9ec 100644 --- a/virtualbox.spec +++ b/virtualbox.spec @@ -158,6 +158,8 @@ Patch136: VirtualBox-6.1.4-VBoxClient-vmsvga-x11-crash.patch Patch137: fix-missing-includes-with-qt-5.15.patch # Fix builds with GCC10 Patch138: fixes_for_gcc10.patch +# Change default display type +Patch139: change_default_display.patch Patch999: virtualbox-fix-ui-background-color.patch # BuildRequires: LibVNCServer-devel @@ -466,6 +468,7 @@ as an "extpack" for VirtualBox. The implementation is licensed under GPL. %patch136 -p1 %patch137 -p1 %patch138 -p1 +%patch139 -p1 # make VB UI background colors look sane again %patch999 -p1 From 78e20f7c06e1421df15c683668c7bffb67e32d5c271ca02706f2e7f91824fde8 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Mon, 13 Apr 2020 17:13:07 +0000 Subject: [PATCH 2/2] Accepting request 793204 from home:frispete:kernel Dear Larry, here's a small adjustment, that allows building current virtualbox for newer kernels on older distributions. - apply fixes for kernel 5.6 unconditionally - adjust fixes_for_5.6.patch in such a way, it can be applied unconditionally (in order to support builds for newer kernel with older distributions) OBS-URL: https://build.opensuse.org/request/show/793204 OBS-URL: https://build.opensuse.org/package/show/Virtualization/virtualbox?expand=0&rev=546 --- fixes_for_5.6.patch | 2 +- virtualbox.changes | 7 +++++++ virtualbox.spec | 2 -- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/fixes_for_5.6.patch b/fixes_for_5.6.patch index a731002..934b2fc 100644 --- a/fixes_for_5.6.patch +++ b/fixes_for_5.6.patch @@ -49,11 +49,11 @@ Index: VirtualBox-6.1.2/include/iprt/time.h + * time handling macros were hidden. Thus, user- and kernel-space + * names are different. + */ -+#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0) ++#include +#define timespec __kernel_old_timespec +#define ktime_get_ts ktime_get_ts64 +#undef time_t diff --git a/virtualbox.changes b/virtualbox.changes index 2ce8b1d..067fdbc 100644 --- a/virtualbox.changes +++ b/virtualbox.changes @@ -9,6 +9,13 @@ Thu Apr 9 21:49:36 UTC 2020 - Larry Finger - Makefile in the kernel-host-source package has a typo bug fixed (boo#1168910) and a large number of warnings are fixed. +------------------------------------------------------------------- +Sun Apr 5 18:05:53 UTC 2020 - Hans-Peter Jansen + +- apply fixes for kernel 5.6 unconditionally +- adjust fixes_for_5.6.patch in such a way, it can be applied unconditionally + (in order to support builds for newer kernel with older distributions) + ------------------------------------------------------------------- Sun Mar 29 19:20:48 UTC 2020 - Larry Finger diff --git a/virtualbox.spec b/virtualbox.spec index 7c9e9ec..9677c30 100644 --- a/virtualbox.spec +++ b/virtualbox.spec @@ -462,9 +462,7 @@ as an "extpack" for VirtualBox. The implementation is licensed under GPL. %endif %patch133 -p1 %patch134 -p1 -%if 0%{?suse_version} > 1500 %patch135 -p1 -%endif %patch136 -p1 %patch137 -p1 %patch138 -p1