forked from pool/virtualbox
6c3d667234
- Version bump to VirtualBox 7.0.14 (released January 16, 2024 by Oracle)
This is a maintenance release. The following items were fixed and/or added:
Audio: Added more fixes for switching host audio devices on Windows hosts using the WAS backend
3D: Added general improvements
OCI: Fixed wrong guest RAM unit usage in VirtualSystemDescription, memory is provided in bytes, "Byte" is the base unit
Main: OVF Import/Export: Added support for importing and exporting VMs containing NVMe storage controllers (bug #19320)
Main: OVF Import/Export: Added support for exporting a VM which contains a medium inserted into a virtual CD/DVD drive which is attached to a Virtio-SCSI controller
Devices: Fixed a problem where Windows guests "forget" in-progress touch events when the user holds down a finger without moving it for a period of time.
macOS Host USB: Added support for newer storage devices
macOS Host: Fixed memory Leak in the VBoxIntNetSwitch process when VM was configured to use 'Internal Networking' (bug #21752)
Linux Host and Guest: Added initial support for RHEL 9.4 kernel
Linux Guest Additions: Fixed kernel panic on RHEL 8.9 kernel caused by vboxvideo (bugs #10381 and #21911)
Solaris Guest Additions: Added support for the Additions to be installed into an alternate root path ('pkgadd -R')
Solaris Guest Additions: Removed requirement to reboot VM after uninstalling GAs
RDP: Fix possible crash when connecting with the Apple Silicon variant of the Microsoft Remote Desktop application (bug #21820).
BIOS: Fixed handle number used for DMI OEM table (bug #19781)
=======
>>>>>>> ./virtualbox.changes.new
OBS-URL: https://build.opensuse.org/request/show/1142681
OBS-URL: https://build.opensuse.org/package/show/Virtualization/virtualbox?expand=0&rev=720
827 lines
30 KiB
Diff
827 lines
30 KiB
Diff
Index: VirtualBox-7.0.14/src/VBox/HostDrivers/linux/Makefile
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===================================================================
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--- VirtualBox-7.0.14.orig/src/VBox/HostDrivers/linux/Makefile
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+++ VirtualBox-7.0.14/src/VBox/HostDrivers/linux/Makefile
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@@ -43,11 +43,8 @@ obj-m = vboxdrv/
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obj-m += vboxnetflt/
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endif
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ifneq ($(wildcard $(CURDIR)/vboxnetadp/Makefile),)
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-obj-m += vboxnetadp/
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- endif
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- ifneq ($(wildcard $(CURDIR)/vboxpci/Makefile),)
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-obj-m += vboxpci/
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- endif
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+ obj-m += vboxnetadp/
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+endif
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else # ! KERNELRELEASE
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@@ -62,12 +59,14 @@ SUDO :=
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endif
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KBUILD_VERBOSE ?=
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+PWD ?= $(shell pwd)
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+
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.PHONY: all install clean check unload load \
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- vboxdrv vboxnetflt vboxnetadp vboxpci \
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- install-vboxdrv install-vboxnetflt install-vboxnetadp install-vboxpci \
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- clean-vboxdrv clean-vboxnetflt clean-vboxnetadp clean-vboxpci
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+ vboxdrv vboxnetflt vboxnetadp \
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+ install-vboxdrv install-vboxnetflt install-vboxnetadp \
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+ clean-vboxdrv clean-vboxnetflt clean-vboxnetadp
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-all: vboxdrv vboxnetflt vboxnetadp vboxpci
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+all: vboxdrv vboxnetflt vboxnetadp
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# We want to build on Linux 2.6.18 and later kernels.
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KERN_VER ?= $(shell uname -r)
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@@ -81,56 +80,38 @@ vboxdrv:
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vboxnetflt: vboxdrv
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+@if [ -d vboxnetflt ]; then \
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- if [ -f vboxdrv/Module.symvers ]; then \
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- cp vboxdrv/Module.symvers vboxnetflt; \
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- fi; \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxdrv/Module.symvers; \
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echo "=== Building 'vboxnetflt' module ==="; \
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- $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxnetflt/Module.symvers) -C vboxnetflt || exit 1; \
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+ $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxdrv/Module.symvers) -C vboxnetflt || exit 1; \
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cp vboxnetflt/vboxnetflt.ko .; \
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echo; \
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fi
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vboxnetadp: vboxdrv
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+@if [ -d vboxnetadp ]; then \
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- if [ -f vboxdrv/Module.symvers ]; then \
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- cp vboxdrv/Module.symvers vboxnetadp; \
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- fi; \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxdrv/Module.symvers; \
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echo "=== Building 'vboxnetadp' module ==="; \
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- $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxnetadp/Module.symvers) -C vboxnetadp || exit 1; \
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+ $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxdrv/Module.symvers) -C vboxnetadp || exit 1; \
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cp vboxnetadp/vboxnetadp.ko .; \
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echo; \
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fi
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-vboxpci: vboxdrv
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- +@if [ -d vboxpci ]; then \
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- if [ -f vboxdrv/Module.symvers ]; then \
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- cp vboxdrv/Module.symvers vboxpci; \
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- fi; \
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- echo "=== Building 'vboxpci' module ==="; \
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- $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxpci/Module.symvers) -C vboxpci || exit 1; \
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- cp vboxpci/vboxpci.ko .; \
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- echo; \
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- fi
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-
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install-vboxdrv:
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+@$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxdrv install
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install-vboxnetflt:
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+@if [ -d vboxnetflt ]; then \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxdrv/Module.symvers; \
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$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxnetflt install; \
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fi
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install-vboxnetadp:
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+@if [ -d vboxnetadp ]; then \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxdrv/Module.symvers; \
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$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxnetadp install; \
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fi
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-install-vboxpci:
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- +@if [ -d vboxpci ]; then \
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- $(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxpci install; \
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- fi
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-
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-install: install-vboxdrv install-vboxnetflt install-vboxnetadp install-vboxpci
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+install: install-vboxdrv install-vboxnetflt install-vboxnetadp
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# Look for wrapper modules, sorting them so vmmr0 is first.
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VBOX_WRAPPER_DIRS := $(notdir $(wildcard $(CURDIR)/vbox_*))
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@@ -140,6 +121,9 @@ VBOX_WRAPPER_DIRS := $(filter vbox_vmmr0
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define wrapper_template
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$(wrapper): $(subst $(wrapper),,vbox_vmmr0)
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+$$(MAKE) KBUILD_VERBOSE=$$(KBUILD_VERBOSE) -C $(wrapper)/
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+vboxnetflt:
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+vboxnetadp:
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+install:
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load-$(wrapper): $(subst load-$(wrapper),,load-vbox_vmmr0)
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@if ! grep -q "^$(wrapper) " /proc/modules; then \
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@@ -217,19 +201,13 @@ clean-vboxnetadp:
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fi
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rm -rf vboxnetadp.ko
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-clean-vboxpci:
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- +@if [ -d vboxpci ]; then \
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- $(MAKE) -C vboxpci clean; \
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- fi
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- rm -f vboxpci.ko
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-
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-clean: clean-vboxdrv clean-vboxnetflt clean-vboxnetadp clean-vboxpci
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+clean: clean-vboxdrv clean-vboxnetflt clean-vboxnetadp
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check:
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+@$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxdrv check
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unload:
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- @for module in vboxpci vboxnetadp vboxnetflt vboxdrv; do \
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+ @for module in vboxnetadp vboxnetflt vboxdrv; do \
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if grep "^$$module " /proc/modules >/dev/null; then \
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echo "Removing previously installed $$module module"; \
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$(SUDO) /sbin/rmmod $$module; \
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@@ -237,7 +215,7 @@ unload:
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done
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load: unload
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- @for module in vboxdrv vboxnetflt vboxnetadp vboxpci; do \
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+ @for module in vboxdrv vboxnetflt vboxnetadp; do \
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if test -f $$module.ko; then \
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echo "Installing $$module module"; \
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$(SUDO) /sbin/insmod $$module.ko; \
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Index: VirtualBox-7.0.14/src/VBox/Additions/linux/Makefile
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===================================================================
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--- VirtualBox-7.0.14.orig/src/VBox/Additions/linux/Makefile
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+++ VirtualBox-7.0.14/src/VBox/Additions/linux/Makefile
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@@ -34,6 +34,7 @@ obj-m = vboxguest/ vboxsf/ vboxvideo/
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else # ! KERNELRELEASE
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KBUILD_VERBOSE =
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+PWD ?= $(shell pwd)
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ifeq ($(KBUILD_VERBOSE),)
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VBOX_QUIET := @
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VBOX_QUIET_SH := @
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@@ -59,6 +60,7 @@ vboxsf: vboxguest
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if [ -f vboxguest/Module.symvers ]; then \
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cp vboxguest/Module.symvers vboxsf; \
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fi; \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxvideo/Module.symvers; \
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echo "=== Building 'vboxsf' module ==="; \
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$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) KBUILD_EXTRA_SYMBOLS=$(abspath vboxsf/Module.symvers) -C vboxsf || exit 1; \
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if [ -f vboxsf/vboxsf.ko ]; then \
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@@ -71,6 +73,9 @@ vboxsf: vboxguest
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vboxvideo:
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+ $(VBOX_QUIET_SH)if [ -d vboxvideo ]; then \
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+ if [ -f vboxguest/Module.symvers ]; then \
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+ cp vboxguest/Module.symvers vboxvideo; \
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+ fi; \
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echo "=== Building 'vboxvideo' module ==="; \
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$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxvideo || exit 1; \
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if [ -f vboxvideo/vboxvideo.ko ]; then \
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@@ -86,11 +91,13 @@ install-vboxguest:
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install-vboxsf:
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+ $(VBOX_QUIET_SH)if [ -d vboxsf ]; then \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxsf/Module.symvers; \
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$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxsf install; \
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fi
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install-vboxvideo:
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+ $(VBOX_QUIET_SH)if [ -d vboxvideo ]; then \
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+ export KBUILD_EXTRA_SYMBOLS=${PWD}/vboxvideo/Module.symvers; \
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$(MAKE) KBUILD_VERBOSE=$(KBUILD_VERBOSE) -C vboxvideo install; \
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fi
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Index: VirtualBox-7.0.14/include/iprt/x86.h
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===================================================================
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--- VirtualBox-7.0.14.orig/include/iprt/x86.h
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+++ VirtualBox-7.0.14/include/iprt/x86.h
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@@ -937,37 +937,59 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
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* reserved flags.
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* @{ */
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/** Bit 0 - PE - Protection Enabled */
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+#ifndef X86_CR0_PE
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#define X86_CR0_PE RT_BIT_32(0)
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+#endif
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#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
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/** Bit 1 - MP - Monitor Coprocessor */
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+#ifndef X86_CR0_MP
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#define X86_CR0_MP RT_BIT_32(1)
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+#endif
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#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
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/** Bit 2 - EM - Emulation. */
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+#ifndef X86_CR0_EM
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#define X86_CR0_EM RT_BIT_32(2)
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+#endif
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#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
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/** Bit 3 - TS - Task Switch. */
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+#ifndef X86_CR0_TS
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#define X86_CR0_TS RT_BIT_32(3)
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+#endif
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#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
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/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
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+#ifndef X86_CR0_ET
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#define X86_CR0_ET RT_BIT_32(4)
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+#endif
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#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
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/** Bit 5 - NE - Numeric error (486+). */
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+#ifndef X86_CR0_NE
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#define X86_CR0_NE RT_BIT_32(5)
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+#endif
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#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
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/** Bit 16 - WP - Write Protect (486+). */
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+#ifndef X86_CR0_WP
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#define X86_CR0_WP RT_BIT_32(16)
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+#endif
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#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
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/** Bit 18 - AM - Alignment Mask (486+). */
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+#ifndef X86_CR0_AM
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#define X86_CR0_AM RT_BIT_32(18)
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+#endif
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#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
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/** Bit 29 - NW - Not Write-though (486+). */
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+#ifndef X86_CR0_NW
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#define X86_CR0_NW RT_BIT_32(29)
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+#endif
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#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
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/** Bit 30 - WP - Cache Disable (486+). */
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+#ifndef X86_CR0_CD
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#define X86_CR0_CD RT_BIT_32(30)
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+#endif
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#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
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/** Bit 31 - PG - Paging. */
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+#ifndef X86_CR0_PG
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#define X86_CR0_PG RT_BIT_32(31)
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+#endif
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#define X86_CR0_PAGING RT_BIT_32(31)
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#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
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/** @} */
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@@ -976,9 +998,13 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
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/** @name CR3
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* @{ */
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/** Bit 3 - PWT - Page-level Writes Transparent. */
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+#ifndef X86_CR3_PWT
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#define X86_CR3_PWT RT_BIT_32(3)
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+#endif
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/** Bit 4 - PCD - Page-level Cache Disable. */
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+#ifndef X86_CR3_PCD
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#define X86_CR3_PCD RT_BIT_32(4)
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+#endif
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/** Bits 12-31 - - Page directory page number. */
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#define X86_CR3_PAGE_MASK (0xfffff000)
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/** Bits 5-31 - - PAE Page directory page number. */
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@@ -997,46 +1023,84 @@ typedef const X86CPUIDFEATEDX *PCX86CPUI
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/** @name CR4
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* @{ */
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/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
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+#ifndef X86_CR4_VME
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#define X86_CR4_VME RT_BIT_32(0)
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+#endif
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/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
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+#ifndef X86_CR4_PVI
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#define X86_CR4_PVI RT_BIT_32(1)
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+#endif
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/** Bit 2 - TSD - Time Stamp Disable. */
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+#ifndef X86_CR4_TSD
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#define X86_CR4_TSD RT_BIT_32(2)
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+#endif
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/** Bit 3 - DE - Debugging Extensions. */
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+#ifndef X86_CR4_DE
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#define X86_CR4_DE RT_BIT_32(3)
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+#endif
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/** Bit 4 - PSE - Page Size Extension. */
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+#ifndef X86_CR4_PSE
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#define X86_CR4_PSE RT_BIT_32(4)
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+#endif
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/** Bit 5 - PAE - Physical Address Extension. */
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+#ifndef X86_CR4_PAE
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#define X86_CR4_PAE RT_BIT_32(5)
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+#endif
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/** Bit 6 - MCE - Machine-Check Enable. */
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+#ifndef X86_CR4_MCE
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#define X86_CR4_MCE RT_BIT_32(6)
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+#endif
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/** Bit 7 - PGE - Page Global Enable. */
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+#ifndef X86_CR4_PGE
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#define X86_CR4_PGE RT_BIT_32(7)
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+#endif
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/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
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+#ifndef X86_CR4_PCE
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#define X86_CR4_PCE RT_BIT_32(8)
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+#endif
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/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
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+#ifndef X86_CR4_OSFXSR
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#define X86_CR4_OSFXSR RT_BIT_32(9)
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+#endif
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/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
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#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
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/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
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+#ifndef X86_CR4_UMIP
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#define X86_CR4_UMIP RT_BIT_32(11)
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+#endif
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/** Bit 13 - VMXE - VMX mode is enabled. */
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+#ifndef X86_CR4_VMXE
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#define X86_CR4_VMXE RT_BIT_32(13)
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+#endif
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/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
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+#ifndef X86_CR4_SMXE
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#define X86_CR4_SMXE RT_BIT_32(14)
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+#endif
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/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
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+#ifndef X86_CR4_FSGSBASE
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#define X86_CR4_FSGSBASE RT_BIT_32(16)
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+#endif
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/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
|
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+#ifndef X86_CR4_PCIDE
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#define X86_CR4_PCIDE RT_BIT_32(17)
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+#endif
|
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/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
|
|
* extended states. */
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+#ifndef X86_CR4_OSXSAVE
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#define X86_CR4_OSXSAVE RT_BIT_32(18)
|
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+#endif
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/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
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+#ifndef X86_CR4_SMEP
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|
#define X86_CR4_SMEP RT_BIT_32(20)
|
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+#endif
|
|
/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
|
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+#ifndef X86_CR4_SMAP
|
|
#define X86_CR4_SMAP RT_BIT_32(21)
|
|
+#endif
|
|
/** Bit 22 - PKE - Protection Key Enable. */
|
|
+#ifndef X86_CR4_PKE
|
|
#define X86_CR4_PKE RT_BIT_32(22)
|
|
+#endif
|
|
/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
|
|
#define X86_CR4_CET RT_BIT_32(23)
|
|
/** @} */
|
|
@@ -1267,12 +1331,16 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
/** Machine check type register (P5). */
|
|
#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
|
|
/** Time Stamp Counter. */
|
|
+#ifndef MSR_IA32_TSC
|
|
#define MSR_IA32_TSC 0x10
|
|
+#endif
|
|
#define MSR_IA32_CESR UINT32_C(0x00000011)
|
|
#define MSR_IA32_CTR0 UINT32_C(0x00000012)
|
|
#define MSR_IA32_CTR1 UINT32_C(0x00000013)
|
|
|
|
+#ifndef MSR_IA32_PLATFORM_ID
|
|
#define MSR_IA32_PLATFORM_ID 0x17
|
|
+#endif
|
|
|
|
#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
|
|
# define MSR_IA32_APICBASE 0x1b
|
|
@@ -1298,7 +1366,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_CORE_THREAD_COUNT 0x35
|
|
|
|
/** CPU Feature control. */
|
|
+#ifndef MSR_IA32_FEATURE_CONTROL
|
|
#define MSR_IA32_FEATURE_CONTROL 0x3A
|
|
+#endif
|
|
/** Feature control - Lock MSR from writes (R/W0). */
|
|
#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
|
|
/** Feature control - Enable VMX inside SMX operation (R/WL). */
|
|
@@ -1323,11 +1393,15 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
|
|
|
|
/** Per-processor TSC adjust MSR. */
|
|
+#ifndef MSR_IA32_TSC_ADJUST
|
|
#define MSR_IA32_TSC_ADJUST 0x3B
|
|
+#endif
|
|
|
|
/** Spectre control register.
|
|
* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
|
|
+#ifndef MSR_IA32_SPEC_CTRL
|
|
#define MSR_IA32_SPEC_CTRL 0x48
|
|
+#endif
|
|
/** IBRS - Indirect branch restricted speculation. */
|
|
#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
|
|
/** STIBP - Single thread indirect branch predictors. */
|
|
@@ -1337,7 +1411,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
|
|
/** Prediction command register.
|
|
* Write only, logical processor scope, no state since write only. */
|
|
+#ifndef MSR_IA32_PRED_CMD
|
|
#define MSR_IA32_PRED_CMD 0x49
|
|
+#endif
|
|
/** IBPB - Indirect branch prediction barrie when written as 1. */
|
|
#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
|
|
|
|
@@ -1348,7 +1424,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_IA32_BIOS_SIGN_ID 0x8B
|
|
|
|
/** SMM monitor control. */
|
|
+#ifndef MSR_IA32_SMM_MONITOR_CTL
|
|
#define MSR_IA32_SMM_MONITOR_CTL 0x9B
|
|
+#endif
|
|
/** SMM control - Valid. */
|
|
#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
|
|
/** SMM control - VMXOFF unblocks SMI. */
|
|
@@ -1357,10 +1435,14 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
|
|
|
|
/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
|
|
+#ifndef MSR_IA32_SMBASE
|
|
#define MSR_IA32_SMBASE 0x9E
|
|
+#endif
|
|
|
|
/** General performance counter no. 0. */
|
|
+#ifndef MSR_IA32_PMC0
|
|
#define MSR_IA32_PMC0 0xC1
|
|
+#endif
|
|
/** General performance counter no. 1. */
|
|
#define MSR_IA32_PMC1 0xC2
|
|
/** General performance counter no. 2. */
|
|
@@ -1383,18 +1465,26 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_IA32_FSB_CLOCK_STS 0xCD
|
|
|
|
/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
|
|
+#ifndef MSR_PKG_CST_CONFIG_CONTROL
|
|
#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
|
|
+#endif
|
|
|
|
/** C0 Maximum Frequency Clock Count */
|
|
+#ifndef MSR_IA32_MPERF
|
|
#define MSR_IA32_MPERF 0xE7
|
|
+#endif
|
|
/** C0 Actual Frequency Clock Count */
|
|
+#ifndef MSR_IA32_APERF
|
|
#define MSR_IA32_APERF 0xE8
|
|
+#endif
|
|
|
|
/** MTRR Capabilities. */
|
|
#define MSR_IA32_MTRR_CAP 0xFE
|
|
|
|
/** Architecture capabilities (bugfixes). */
|
|
+#ifndef MSR_IA32_ARCH_CAPABILITIES
|
|
#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
|
|
+#endif
|
|
/** CPU is no subject to meltdown problems. */
|
|
#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
|
|
/** CPU has better IBRS and you can leave it on all the time. */
|
|
@@ -1408,7 +1498,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
|
|
|
|
/** Flush command register. */
|
|
+#ifndef MSR_IA32_FLUSH_CMD
|
|
#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
|
|
+#endif
|
|
/** Flush the level 1 data cache when this bit is written. */
|
|
#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
|
|
|
|
@@ -1429,14 +1521,20 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#endif
|
|
|
|
/** Machine Check Global Capabilities Register. */
|
|
+#ifndef MSR_IA32_MCG_CAP
|
|
#define MSR_IA32_MCG_CAP 0x179
|
|
+#endif
|
|
/** Machine Check Global Status Register. */
|
|
+#ifndef MSR_IA32_MCG_STATUS
|
|
#define MSR_IA32_MCG_STATUS 0x17A
|
|
+#endif
|
|
/** Machine Check Global Control Register. */
|
|
#define MSR_IA32_MCG_CTRL 0x17B
|
|
|
|
/** Page Attribute Table. */
|
|
+#ifndef MSR_IA32_CR_PAT
|
|
#define MSR_IA32_CR_PAT 0x277
|
|
+#endif
|
|
/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
|
|
* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
|
|
#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
|
|
@@ -1455,36 +1553,58 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_FLEX_RATIO 0x194
|
|
/** Performance state value and starting with Intel core more.
|
|
* Apple uses the >=core features to determine TSC granularity on older CPUs. */
|
|
+#ifndef MSR_IA32_PERF_STATUS
|
|
#define MSR_IA32_PERF_STATUS 0x198
|
|
+#endif
|
|
+#ifndef MSR_IA32_PERF_CTL
|
|
#define MSR_IA32_PERF_CTL 0x199
|
|
+#endif
|
|
+#ifndef MSR_IA32_THERM_STATUS
|
|
#define MSR_IA32_THERM_STATUS 0x19c
|
|
+#endif
|
|
|
|
/** Offcore response event select registers. */
|
|
+#ifndef MSR_OFFCORE_RSP_0
|
|
#define MSR_OFFCORE_RSP_0 0x1a6
|
|
+#endif
|
|
+#ifndef MSR_OFFCORE_RSP_1
|
|
#define MSR_OFFCORE_RSP_1 0x1a7
|
|
+#endif
|
|
|
|
/** Enable misc. processor features (R/W). */
|
|
+#ifndef MSR_IA32_MISC_ENABLE
|
|
#define MSR_IA32_MISC_ENABLE 0x1A0
|
|
+#endif
|
|
/** Enable fast-strings feature (for REP MOVS and REP STORS). */
|
|
#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
|
|
/** Automatic Thermal Control Circuit Enable (R/W). */
|
|
+#ifndef MSR_IA32_MISC_ENABLE_TCC
|
|
#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
|
|
+#endif
|
|
/** Performance Monitoring Available (R). */
|
|
#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
|
|
/** Branch Trace Storage Unavailable (R/O). */
|
|
+#ifndef MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
|
|
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
|
|
+#endif
|
|
/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
|
|
+#ifndef MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
|
|
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
|
|
+#endif
|
|
/** Enhanced Intel SpeedStep Technology Enable (R/W). */
|
|
#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
|
|
/** If MONITOR/MWAIT is supported (R/W). */
|
|
#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
|
|
/** Limit CPUID Maxval to 3 leafs (R/W). */
|
|
+#ifndef MSR_IA32_MISC_ENABLE_LIMIT_CPUID
|
|
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
|
|
+#endif
|
|
/** When set to 1, xTPR messages are disabled (R/W). */
|
|
#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
|
|
/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
|
|
+#ifndef MSR_IA32_MISC_ENABLE_XD_DISABLE
|
|
#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
|
|
+#endif
|
|
|
|
/** Trace/Profile Resource Control (R/W) */
|
|
#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
|
|
@@ -1665,7 +1785,9 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
/** @} */
|
|
|
|
/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
|
|
+#ifndef MSR_IA32_TSX_CTRL
|
|
#define MSR_IA32_TSX_CTRL 0x122
|
|
+#endif
|
|
|
|
/** Variable range MTRRs.
|
|
* @{ */
|
|
@@ -1715,93 +1837,171 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
|
|
|
|
/** Precise Event Based sampling (Intel only). */
|
|
+#ifndef MSR_IA32_PEBS_ENABLE
|
|
#define MSR_IA32_PEBS_ENABLE 0x3F1
|
|
+#endif
|
|
|
|
+#ifndef MSR_DRAM_POWER_LIMIT
|
|
#define MSR_IA32_MC0_CTL 0x400
|
|
+#endif
|
|
+#ifndef MSR_IA32_MC0_STATUS
|
|
#define MSR_IA32_MC0_STATUS 0x401
|
|
+#endif
|
|
|
|
/** Basic VMX information. */
|
|
+#ifndef MSR_IA32_VMX_BASIC
|
|
#define MSR_IA32_VMX_BASIC 0x480
|
|
+#endif
|
|
/** Allowed settings for pin-based VM execution controls. */
|
|
+#ifndef MSR_IA32_VMX_PINBASED_CTLS
|
|
#define MSR_IA32_VMX_PINBASED_CTLS 0x481
|
|
+#endif
|
|
/** Allowed settings for proc-based VM execution controls. */
|
|
+#ifndef MSR_IA32_VMX_PROCBASED_CTLS
|
|
#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
|
|
+#endif
|
|
/** Allowed settings for the VM-exit controls. */
|
|
+#ifndef MSR_IA32_VMX_EXIT_CTLS
|
|
#define MSR_IA32_VMX_EXIT_CTLS 0x483
|
|
+#endif
|
|
/** Allowed settings for the VM-entry controls. */
|
|
+#ifndef MSR_IA32_VMX_ENTRY_CTLS
|
|
#define MSR_IA32_VMX_ENTRY_CTLS 0x484
|
|
+#endif
|
|
/** Misc VMX info. */
|
|
+#ifndef MSR_IA32_VMX_MISC
|
|
#define MSR_IA32_VMX_MISC 0x485
|
|
+#endif
|
|
/** Fixed cleared bits in CR0. */
|
|
+#ifndef MSR_IA32_VMX_CR0_FIXED0
|
|
#define MSR_IA32_VMX_CR0_FIXED0 0x486
|
|
+#endif
|
|
/** Fixed set bits in CR0. */
|
|
+#ifndef MSR_IA32_VMX_CR0_FIXED1
|
|
#define MSR_IA32_VMX_CR0_FIXED1 0x487
|
|
+#endif
|
|
/** Fixed cleared bits in CR4. */
|
|
+#ifndef MSR_IA32_VMX_CR4_FIXED0
|
|
#define MSR_IA32_VMX_CR4_FIXED0 0x488
|
|
+#endif
|
|
/** Fixed set bits in CR4. */
|
|
+#ifndef MSR_IA32_VMX_CR4_FIXED1
|
|
#define MSR_IA32_VMX_CR4_FIXED1 0x489
|
|
+#endif
|
|
/** Information for enumerating fields in the VMCS. */
|
|
+#ifndef MSR_IA32_VMX_VMCS_ENUM
|
|
#define MSR_IA32_VMX_VMCS_ENUM 0x48A
|
|
+#endif
|
|
/** Allowed settings for secondary processor-based VM-execution controls. */
|
|
+#ifndef MSR_IA32_VMX_PROCBASED_CTLS2
|
|
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
|
|
+#endif
|
|
/** EPT capabilities. */
|
|
+#ifndef MSR_IA32_VMX_EPT_VPID_CAP
|
|
#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
|
|
+#endif
|
|
/** Allowed settings of all pin-based VM execution controls. */
|
|
+#ifndef MSR_IA32_VMX_TRUE_PINBASED_CTLS
|
|
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
|
|
+#endif
|
|
/** Allowed settings of all proc-based VM execution controls. */
|
|
+#ifndef MSR_IA32_VMX_TRUE_PROCBASED_CTLS
|
|
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
|
|
+#endif
|
|
/** Allowed settings of all VMX exit controls. */
|
|
+#ifndef MSR_IA32_VMX_TRUE_EXIT_CTLS
|
|
#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
|
|
+#endif
|
|
/** Allowed settings of all VMX entry controls. */
|
|
+#ifndef MSR_IA32_VMX_TRUE_ENTRY_CTLS
|
|
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
|
|
+#endif
|
|
/** Allowed settings for the VM-function controls. */
|
|
+#ifndef MSR_IA32_VMX_VMFUNC
|
|
#define MSR_IA32_VMX_VMFUNC 0x491
|
|
/** Tertiary processor-based VM execution controls. */
|
|
#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
|
|
/** Secondary VM-exit controls. */
|
|
#define MSR_IA32_VMX_EXIT_CTLS2 0x493
|
|
+#endif
|
|
|
|
/** Intel PT - Enable and control for trace packet generation. */
|
|
+#ifndef MSR_IA32_RTIT_CTL
|
|
#define MSR_IA32_RTIT_CTL 0x570
|
|
+#endif
|
|
|
|
/** DS Save Area (R/W). */
|
|
+#ifndef MSR_IA32_DS_AREA
|
|
#define MSR_IA32_DS_AREA 0x600
|
|
+#endif
|
|
/** Running Average Power Limit (RAPL) power units. */
|
|
+#ifndef MSR_RAPL_POWER_UNIT
|
|
#define MSR_RAPL_POWER_UNIT 0x606
|
|
+#endif
|
|
/** Package C3 Interrupt Response Limit. */
|
|
+#ifndef MSR_PKGC3_IRTL
|
|
#define MSR_PKGC3_IRTL 0x60a
|
|
+#endif
|
|
/** Package C6/C7S Interrupt Response Limit 1. */
|
|
#define MSR_PKGC_IRTL1 0x60b
|
|
/** Package C6/C7S Interrupt Response Limit 2. */
|
|
#define MSR_PKGC_IRTL2 0x60c
|
|
/** Package C2 Residency Counter. */
|
|
+#ifndef MSR_PKG_C2_RESIDENCY
|
|
#define MSR_PKG_C2_RESIDENCY 0x60d
|
|
+#endif
|
|
/** PKG RAPL Power Limit Control. */
|
|
+#ifndef MSR_PKG_POWER_LIMIT
|
|
#define MSR_PKG_POWER_LIMIT 0x610
|
|
+#endif
|
|
/** PKG Energy Status. */
|
|
+#ifndef MSR_PKG_ENERGY_STATUS
|
|
#define MSR_PKG_ENERGY_STATUS 0x611
|
|
+#endif
|
|
/** PKG Perf Status. */
|
|
+#ifndef MSR_PKG_PERF_STATUS
|
|
#define MSR_PKG_PERF_STATUS 0x613
|
|
+#endif
|
|
/** PKG RAPL Parameters. */
|
|
+#ifndef MSR_PKG_POWER_INFO
|
|
#define MSR_PKG_POWER_INFO 0x614
|
|
+#endif
|
|
/** DRAM RAPL Power Limit Control. */
|
|
+#ifndef MSR_DRAM_POWER_LIMIT
|
|
#define MSR_DRAM_POWER_LIMIT 0x618
|
|
+#endif
|
|
/** DRAM Energy Status. */
|
|
+#ifndef MSR_DRAM_ENERGY_STATUS
|
|
#define MSR_DRAM_ENERGY_STATUS 0x619
|
|
+#endif
|
|
/** DRAM Performance Throttling Status. */
|
|
+#ifndef MSR_DRAM_PERF_STATUS
|
|
#define MSR_DRAM_PERF_STATUS 0x61b
|
|
+#endif
|
|
/** DRAM RAPL Parameters. */
|
|
+#ifndef MSR_DRAM_POWER_INFO
|
|
#define MSR_DRAM_POWER_INFO 0x61c
|
|
+#endif
|
|
/** Package C10 Residency Counter. */
|
|
+#ifndef MSR_PKG_C10_RESIDENCY
|
|
#define MSR_PKG_C10_RESIDENCY 0x632
|
|
+#endif
|
|
/** PP0 Energy Status. */
|
|
+#ifndef MSR_PP0_ENERGY_STATUS
|
|
#define MSR_PP0_ENERGY_STATUS 0x639
|
|
+#endif
|
|
/** PP1 Energy Status. */
|
|
+#ifndef MSR_PP1_ENERGY_STATUS
|
|
#define MSR_PP1_ENERGY_STATUS 0x641
|
|
+#endif
|
|
/** Turbo Activation Ratio. */
|
|
+#ifndef MSR_TURBO_ACTIVATION_RATIO
|
|
#define MSR_TURBO_ACTIVATION_RATIO 0x64c
|
|
+#endif
|
|
/** Core Performance Limit Reasons. */
|
|
+#ifndef MSR_CORE_PERF_LIMIT_REASONS
|
|
#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
|
|
+#endif
|
|
|
|
/** X2APIC MSR range start. */
|
|
#define MSR_IA32_X2APIC_START 0x800
|
|
@@ -1936,23 +2136,47 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
|
|
/** The mask which give the SYSCALL EIP. */
|
|
#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
|
|
/** K6 WHCR - Write Handling Control Register. */
|
|
+#ifndef MSR_K6_WHCR
|
|
#define MSR_K6_WHCR UINT32_C(0xc0000082)
|
|
+#endif
|
|
/** K6 UWCCR - UC/WC Cacheability Control Register. */
|
|
+#ifndef MSR_K6_UWCCR
|
|
#define MSR_K6_UWCCR UINT32_C(0xc0000085)
|
|
+#endif
|
|
/** K6 PSOR - Processor State Observability Register. */
|
|
+#ifndef MSR_K6_PSOR
|
|
#define MSR_K6_PSOR UINT32_C(0xc0000087)
|
|
+#endif
|
|
/** K6 PFIR - Page Flush/Invalidate Register. */
|
|
+#ifndef MSR_K6_PFIR
|
|
#define MSR_K6_PFIR UINT32_C(0xc0000088)
|
|
+#endif
|
|
|
|
/** Performance counter MSRs. (AMD only) */
|
|
+#ifndef MSR_K7_EVNTSEL0
|
|
#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
|
|
+#endif
|
|
+#ifndef MSR_K7_EVNTSEL1
|
|
#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
|
|
+#endif
|
|
+#ifndef MSR_K7_EVNTSEL2
|
|
#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
|
|
+#endif
|
|
+#ifndef MSR_K7_EVNTSEL3
|
|
#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
|
|
+#endif
|
|
+#ifndef MSR_K7_PERFCTR0
|
|
#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
|
|
+#endif
|
|
+#ifndef MSR_K7_PERFCTR1
|
|
#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
|
|
+#endif
|
|
+#ifndef MSR_K7_PERFCTR2
|
|
#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
|
|
+#endif
|
|
+#ifndef MSR_K7_PERFCTR3
|
|
#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
|
|
+#endif
|
|
|
|
/** K8 LSTAR - Long mode SYSCALL target (RIP). */
|
|
#define MSR_K8_LSTAR UINT32_C(0xc0000082)
|
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@@ -1968,14 +2192,20 @@ AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C
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#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
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/** K8 TSC_AUX - Used with RDTSCP. */
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#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
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+#ifndef MSR_K8_SYSCFG
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#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
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+#endif
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#define MSR_K8_HWCR UINT32_C(0xc0010015)
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#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
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#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
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#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
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#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
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+#ifndef MSR_K8_TOP_MEM1
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#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
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+#endif
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+#ifndef MSR_K8_TOP_MEM2
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#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
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+#endif
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/** SMM MSRs. */
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#define MSR_K7_SMBASE UINT32_C(0xc0010111)
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Index: VirtualBox-7.0.14/include/VBox/vmm/hm_vmx.h
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===================================================================
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--- VirtualBox-7.0.14.orig/include/VBox/vmm/hm_vmx.h
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+++ VirtualBox-7.0.14/include/VBox/vmm/hm_vmx.h
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@@ -1633,7 +1633,9 @@ AssertCompileSize(VMXABORT, 4);
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/** VMCS (and related regions) memory type - Uncacheable. */
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#define VMX_BASIC_MEM_TYPE_UC 0
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/** VMCS (and related regions) memory type - Write back. */
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+#ifndef VMX_BASIC_MEM_TYPE_WB
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#define VMX_BASIC_MEM_TYPE_WB 6
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+#endif
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/** Width of physical addresses used for VMCS and associated memory regions
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* (1=32-bit, 0=processor's physical address width). */
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#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
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Index: VirtualBox-7.0.14/src/VBox/Additions/linux/drm/vbox_drv.h
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===================================================================
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--- VirtualBox-7.0.14.orig/src/VBox/Additions/linux/drm/vbox_drv.h
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+++ VirtualBox-7.0.14/src/VBox/Additions/linux/drm/vbox_drv.h
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@@ -87,6 +87,12 @@
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#else
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# define RTLNX_RHEL_MAX(a_iMajor, a_iMinor) (0)
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#endif
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+
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+#if defined(CONFIG_SUSE_VERSION)
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+# if CONFIG_SUSE_VERSION == 15 && CONFIG_SUSE_PATCHLEVEL == 1
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+# define OPENSUSE_151
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+# endif
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+#endif
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#if defined(CONFIG_SUSE_VERSION) && CONFIG_SUSE_VERSION == 12 && CONFIG_SUSE_PATCHLEVEL >= 4
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# define SUSE_SLE12
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#endif
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