Don’t provide _bindir/lua5.1

packages.
- Updated to 2.1.20250826 (1756211046)
  * FFI: Fix dangling CType references (again).
  * Avoid out-of-range PC for stack overflow error from snapshot restore.
  * x86/x64: Don't use undefined MUL/IMUL zero flag.
  * Windows: Add lua52compat option to msvcbuild.bat.
- Cherry-pick riscv64-support.patch to add RISC-V support
- Cherry-pick loong64-support.patch to add LoongArch support
- Reapply patches to avoid fuzz and long-term maintenance:
  loong64-support.patch and riscv64-support.patch.

.gitattributes

@@ -21,4 +21,3 @@
 *.xz filter=lfs diff=lfs merge=lfs -text
 *.zip filter=lfs diff=lfs merge=lfs -text
 *.zst filter=lfs diff=lfs merge=lfs -text
-*.changes merge=merge-changes

.gitignore

@@ -1,5 +1 @@
 .osc
-*.obscpio
-*.osc
-_build.*
-.pbuild

baselibs.conf

@@ -1 +1 @@
-libluajit-5_1-2
+libluajit2-5_1-2

loong64-support.patch

@@ -39,9 +39,9 @@ Subject: [PATCH] Add support for LoongArch64
 
 Index: luajit2-2.1-20250826/Makefile
 ===================================================================
---- luajit2-2.1-20250826.orig/Makefile
-+++ luajit2-2.1-20250826/Makefile
-@@ -102,6 +102,7 @@ FILES_JITLIB= bc.lua bcsave.lua dump.lua
+--- luajit2-2.1-20250826.orig/Makefile	2025-10-09 23:13:50.446088447 +0200
++++ luajit2-2.1-20250826/Makefile	2025-10-09 23:13:59.702839100 +0200
+@@ -102,6 +102,7 @@
  	      dis_mips64.lua dis_mips64el.lua \
  	      dis_mips64r6.lua dis_mips64r6el.lua \
  	      dis_riscv.lua dis_riscv64.lua \
@@ -51,8 +51,8 @@ Index: luajit2-2.1-20250826/Makefile
  ifeq (,$(findstring Windows,$(OS)))
 Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.h	2025-10-09 23:13:59.703032143 +0200
 @@ -0,0 +1,443 @@
 +/*
 +** DynASM LoongArch encoding engine.
@@ -499,8 +499,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.h
 +
 Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua	2025-10-09 23:13:59.703286812 +0200
 @@ -0,0 +1,979 @@
 +------------------------------------------------------------------------------
 +-- DynASM LoongArch module.
@@ -1483,9 +1483,9 @@ Index: luajit2-2.1-20250826/dynasm/dasm_loongarch64.lua
 +
 Index: luajit2-2.1-20250826/src/Makefile
 ===================================================================
---- luajit2-2.1-20250826.orig/src/Makefile
-+++ luajit2-2.1-20250826/src/Makefile
-@@ -53,6 +53,7 @@ CCOPT_arm64=
+--- luajit2-2.1-20250826.orig/src/Makefile	2025-10-09 23:13:50.446195839 +0200
++++ luajit2-2.1-20250826/src/Makefile	2025-10-09 23:13:59.703845814 +0200
+@@ -53,6 +53,7 @@
  CCOPT_ppc=
  CCOPT_mips=
  CCOPT_riscv64=
@@ -1493,7 +1493,7 @@ Index: luajit2-2.1-20250826/src/Makefile
  #
  #CCDEBUG=
  # Uncomment the next line to generate debug information:
-@@ -247,6 +248,10 @@ else
+@@ -247,6 +248,10 @@
  ifneq (,$(findstring LJ_TARGET_S390X ,$(TARGET_TESTARCH)))
    TARGET_LJARCH= s390x
  else
@@ -1504,7 +1504,7 @@ Index: luajit2-2.1-20250826/src/Makefile
  ifneq (,$(findstring LJ_TARGET_ARM64 ,$(TARGET_TESTARCH)))
    ifneq (,$(findstring __AARCH64EB__ ,$(TARGET_TESTARCH)))
      TARGET_ARCH= -D__AARCH64EB__=1
-@@ -283,6 +288,7 @@ endif
+@@ -283,6 +288,7 @@
  endif
  endif
  endif
@@ -1512,7 +1512,7 @@ Index: luajit2-2.1-20250826/src/Makefile
  
  ifneq (,$(findstring LJ_TARGET_PS3 1,$(TARGET_TESTARCH)))
    TARGET_SYS= PS3
-@@ -352,7 +358,9 @@ else
+@@ -352,7 +358,9 @@
      # Find out whether the target toolchain always generates unwind tables.
      TARGET_TESTUNWIND=$(shell exec 2>/dev/null; echo 'extern void b(void);int a(void){b();return 0;}' | $(TARGET_CC) -c -x c - -o tmpunwind.o && { grep -qa -e eh_frame -e __unwind_info tmpunwind.o || grep -qU -e eh_frame -e __unwind_info tmpunwind.o; } && echo E; rm -f tmpunwind.o)
      ifneq (,$(findstring E,$(TARGET_TESTUNWIND)))
@@ -1525,9 +1525,9 @@ Index: luajit2-2.1-20250826/src/Makefile
    ifneq (SunOS,$(TARGET_SYS))
 Index: luajit2-2.1-20250826/src/host/buildvm.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/host/buildvm.c
-+++ luajit2-2.1-20250826/src/host/buildvm.c
-@@ -71,6 +71,8 @@ static int collect_reloc(BuildCtx *ctx,
+--- luajit2-2.1-20250826.orig/src/host/buildvm.c	2025-10-09 23:13:50.441017227 +0200
++++ luajit2-2.1-20250826/src/host/buildvm.c	2025-10-09 23:13:59.704043405 +0200
+@@ -71,6 +71,8 @@
  #include "../dynasm/dasm_s390x.h"
  #elif LJ_TARGET_RISCV64
  #include "../dynasm/dasm_riscv.h"
@@ -1538,9 +1538,9 @@ Index: luajit2-2.1-20250826/src/host/buildvm.c
  #endif
 Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c
-+++ luajit2-2.1-20250826/src/host/buildvm_asm.c
-@@ -236,6 +236,15 @@ rv_reloc_err:
+--- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c	2025-10-09 23:13:50.441145889 +0200
++++ luajit2-2.1-20250826/src/host/buildvm_asm.c	2025-10-09 23:13:59.704166306 +0200
+@@ -236,6 +236,15 @@
    	    ins, sym);
      exit(1);
    }
@@ -1558,20 +1558,20 @@ Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
  #endif
 Index: luajit2-2.1-20250826/src/jit/bcsave.lua
 ===================================================================
---- luajit2-2.1-20250826.orig/src/jit/bcsave.lua
-+++ luajit2-2.1-20250826/src/jit/bcsave.lua
-@@ -104,6 +104,7 @@ local map_arch = {
+--- luajit2-2.1-20250826.orig/src/jit/bcsave.lua	2025-10-09 23:13:50.441296523 +0200
++++ luajit2-2.1-20250826/src/jit/bcsave.lua	2025-10-09 23:13:59.704320697 +0200
+@@ -104,6 +104,7 @@
    mips64r6el =	{ e = "le", b = 64, m = 8, f = 0xa0000407, },
    s390x =	{ e = "be", b = 64, m = 22, },
-   riscv64 =     { e = "le", b = 64, m = 243, f = 0x00000004, },
+   riscv64 =    { e = "le", b = 64, m = 243, f = 0x00000004, },
 +  loongarch64 = { e = "le", b = 64, m = 258, f = 0x3},
  }
  
  local map_os = {
 Index: luajit2-2.1-20250826/src/jit/dis_loongarch64.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/jit/dis_loongarch64.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/jit/dis_loongarch64.lua	2025-10-09 23:13:59.704533056 +0200
 @@ -0,0 +1,697 @@
 +----------------------------------------------------------------------------
 +-- LuaJIT LoongArch64 disassembler module.
@@ -2272,9 +2272,9 @@ Index: luajit2-2.1-20250826/src/jit/dis_loongarch64.lua
 +
 Index: luajit2-2.1-20250826/src/lib_jit.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lib_jit.c
-+++ luajit2-2.1-20250826/src/lib_jit.c
-@@ -867,7 +867,8 @@ static uint32_t jit_cpudetect(void)
+--- luajit2-2.1-20250826.orig/src/lib_jit.c	2025-10-09 23:13:50.446361090 +0200
++++ luajit2-2.1-20250826/src/lib_jit.c	2025-10-09 23:13:59.704808515 +0200
+@@ -867,7 +867,8 @@
  #endif
  #elif LJ_TARGET_S390X
    /* No optional CPU features to detect (for now). */
@@ -2286,12 +2286,12 @@ Index: luajit2-2.1-20250826/src/lib_jit.c
  
 Index: luajit2-2.1-20250826/src/lj_arch.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_arch.h
-+++ luajit2-2.1-20250826/src/lj_arch.h
+--- luajit2-2.1-20250826.orig/src/lj_arch.h	2025-10-09 23:13:50.433083022 +0200
++++ luajit2-2.1-20250826/src/lj_arch.h	2025-10-09 23:13:59.704965239 +0200
 @@ -35,6 +35,8 @@
  #define LUAJIT_ARCH_s390x	8
- #define LUAJIT_ARCH_riscv64	9
  #define LUAJIT_ARCH_RISCV64	9
+ #define LUAJIT_ARCH_riscv64	9
 +#define LUAJIT_ARCH_LOONGARCH64	10
 +#define LUAJIT_ARCH_loongarch64	10
  
@@ -2306,7 +2306,7 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
  #else
  #error "Architecture not supported (in this version), see: https://luajit.org/status.html#architectures"
  #endif
-@@ -490,6 +494,20 @@
+@@ -489,6 +493,20 @@
  #define LJ_TARGET_MASKROT	1
  #define LJ_ARCH_NUMMODE		LJ_NUMMODE_DUAL
  
@@ -2327,7 +2327,7 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
  #else
  #error "No target architecture defined"
  #endif
-@@ -520,6 +538,16 @@
+@@ -519,6 +537,16 @@
  #error "Need at least GCC 4.8 or newer"
  #endif
  #endif
@@ -2344,7 +2344,7 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
  #elif !LJ_TARGET_PS3
  #if __clang__
  #if ((__clang_major__ < 3) || ((__clang_major__ == 3) && __clang_minor__ < 5))
-@@ -577,6 +605,10 @@
+@@ -576,6 +604,10 @@
  #if !defined(__riscv_float_abi_double)
  #error "Only RISC-V 64 double float supported for now"
  #endif
@@ -2357,9 +2357,9 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
  
 Index: luajit2-2.1-20250826/src/lj_asm.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_asm.c
-+++ luajit2-2.1-20250826/src/lj_asm.c
-@@ -229,6 +229,8 @@ static Reg rset_pickrandom(ASMState *as,
+--- luajit2-2.1-20250826.orig/src/lj_asm.c	2025-10-09 23:13:50.439989544 +0200
++++ luajit2-2.1-20250826/src/lj_asm.c	2025-10-09 23:13:59.705242972 +0200
+@@ -229,6 +229,8 @@
  #include "lj_emit_mips.h"
  #elif LJ_TARGET_RISCV64
  #include "lj_emit_riscv.h"
@@ -2368,7 +2368,7 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
  #else
  #error "Missing instruction emitter for target CPU"
  #endif
-@@ -1714,6 +1716,8 @@ static void asm_loop(ASMState *as)
+@@ -1714,6 +1716,8 @@
  #include "lj_asm_s390x.h"
  #elif LJ_TARGET_RISCV64
  #include "lj_asm_riscv64.h"
@@ -2379,8 +2379,8 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
  #endif
 Index: luajit2-2.1-20250826/src/lj_asm_loongarch64.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/lj_asm_loongarch64.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/lj_asm_loongarch64.h	2025-10-09 23:14:02.153643630 +0200
 @@ -0,0 +1,1990 @@
 +/*
 +** LoongArch IR assembler (SSA IR -> machine code).
@@ -4374,8 +4374,8 @@ Index: luajit2-2.1-20250826/src/lj_asm_loongarch64.h
 +}
 Index: luajit2-2.1-20250826/src/lj_ccall.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_ccall.c
-+++ luajit2-2.1-20250826/src/lj_ccall.c
+--- luajit2-2.1-20250826.orig/src/lj_ccall.c	2025-10-09 23:13:50.437724513 +0200
++++ luajit2-2.1-20250826/src/lj_ccall.c	2025-10-09 23:14:02.155464354 +0200
 @@ -778,6 +778,95 @@
      } \
    }
@@ -4472,7 +4472,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
  #else
  #error "Missing calling convention definitions for this architecture"
  #endif
-@@ -1191,6 +1280,53 @@ noth:  /* Not a homogeneous float/double
+@@ -1191,6 +1280,53 @@
  
  #endif
  
@@ -4526,7 +4526,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
  /* -- Common C call handling ---------------------------------------------- */
  
  /* Infer the destination CTypeID for a vararg argument.
-@@ -1245,7 +1381,9 @@ static int ccall_set_args(lua_State *L,
+@@ -1245,7 +1381,9 @@
  #if LJ_TARGET_RISCV64
    int nff = 0;
  #endif
@@ -4537,7 +4537,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
    /* Clear unused regs to get some determinism in case of misdeclaration. */
    memset(cc->gpr, 0, sizeof(cc->gpr));
  #if CCALL_NUM_FPR
-@@ -1439,7 +1577,7 @@ static int ccall_set_args(lua_State *L,
+@@ -1439,7 +1577,7 @@
      if (isfp && d->size == sizeof(float))
        ((uint32_t *)dp)[1] = 0xffffffffu;  /* Float NaN boxing */
  #endif
@@ -4546,7 +4546,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
      if ((ctype_isinteger_or_bool(d->info) || ctype_isenum(d->info)
  #if LJ_TARGET_MIPS64
  	 || (isfp && nsp == 0)
-@@ -1487,6 +1625,14 @@ static int ccall_set_args(lua_State *L,
+@@ -1487,6 +1625,14 @@
          ((uint64_t *)dp)[i] = 0xffffffff00000000ul | ((uint32_t *)dp)[i];
        } while (i--);
      }
@@ -4561,7 +4561,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
  #else
      UNUSED(isfp);
  #endif
-@@ -1496,7 +1642,7 @@ static int ccall_set_args(lua_State *L,
+@@ -1496,7 +1642,7 @@
    if ((int32_t)nsp < 0) nsp = 0;
  #endif
  
@@ -4572,9 +4572,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
    cc->nsp = (nsp + CTSIZE_PTR-1) & ~(CTSIZE_PTR-1);
 Index: luajit2-2.1-20250826/src/lj_ccall.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_ccall.h
-+++ luajit2-2.1-20250826/src/lj_ccall.h
-@@ -172,6 +172,21 @@ typedef union FPRArg {
+--- luajit2-2.1-20250826.orig/src/lj_ccall.h	2025-10-09 23:13:50.437992427 +0200
++++ luajit2-2.1-20250826/src/lj_ccall.h	2025-10-09 23:13:59.707230811 +0200
+@@ -172,6 +172,21 @@
    struct { LJ_ENDIAN_LOHI(float f; , float g;) };
  } FPRArg;
  
@@ -4596,7 +4596,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
  #else
  #error "Missing calling convention definitions for this architecture"
  #endif
-@@ -219,7 +234,7 @@ typedef LJ_ALIGN(CCALL_ALIGN_CALLSTATE)
+@@ -219,7 +234,7 @@
    uint8_t resx87;		/* Result on x87 stack: 1:float, 2:double. */
  #elif LJ_TARGET_ARM64
    void *retp;			/* Aggregate return pointer in x8. */
@@ -4607,9 +4607,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
  #if LJ_32
 Index: luajit2-2.1-20250826/src/lj_ccallback.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_ccallback.c
-+++ luajit2-2.1-20250826/src/lj_ccallback.c
-@@ -95,6 +95,10 @@ static MSize CALLBACK_OFS2SLOT(MSize ofs
+--- luajit2-2.1-20250826.orig/src/lj_ccallback.c	2025-10-09 23:13:50.438123303 +0200
++++ luajit2-2.1-20250826/src/lj_ccallback.c	2025-10-09 23:13:59.707376084 +0200
+@@ -95,6 +95,10 @@
  
  #define CALLBACK_MCODE_HEAD		68
  
@@ -4620,7 +4620,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  #else
  
  /* Missing support for this architecture. */
-@@ -330,6 +334,33 @@ static void *callback_mcode_init(global_
+@@ -330,6 +334,33 @@
    }
    return p;
  }
@@ -4654,7 +4654,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  #else
  /* Missing support for this architecture. */
  #define callback_mcode_init(g, p)	(p)
-@@ -632,6 +663,31 @@ void lj_ccallback_mcode_free(CTState *ct
+@@ -632,6 +663,31 @@
      if (ngpr < maxgpr) { sp = &cts->cb.gpr[ngpr++]; goto done; } \
    }
  
@@ -4686,7 +4686,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  #elif LJ_TARGET_RISCV64
  
  #define CALLBACK_HANDLE_REGARG \
-@@ -812,7 +868,7 @@ static void callback_conv_result(CTState
+@@ -812,7 +868,7 @@
          *(int64_t *)dp = (int64_t)*(int32_t *)dp;
      }
  #endif
@@ -4697,8 +4697,8 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  	(LJ_ABI_SOFTFP || ctype_isinteger_or_bool(ctr->info)))
 Index: luajit2-2.1-20250826/src/lj_emit_loongarch64.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/lj_emit_loongarch64.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/lj_emit_loongarch64.h	2025-10-09 23:13:59.707601939 +0200
 @@ -0,0 +1,306 @@
 +/*
 +** LoongArch instruction emitter.
@@ -5008,12 +5008,12 @@ Index: luajit2-2.1-20250826/src/lj_emit_loongarch64.h
 +#define emit_spsub(as, ofs)	emit_addptr(as, RID_SP, -(ofs))
 Index: luajit2-2.1-20250826/src/lj_frame.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_frame.h
-+++ luajit2-2.1-20250826/src/lj_frame.h
-@@ -296,6 +296,15 @@ enum { LJ_CONT_TAILCALL, LJ_CONT_FFI_CAL
- #define CFRAME_OFS_MULTRES	0
- #define CFRAME_SIZE		256
- #define CFRAME_SHIFT_MULTRES	3
+--- luajit2-2.1-20250826.orig/src/lj_frame.h	2025-10-09 23:13:50.434938112 +0200
++++ luajit2-2.1-20250826/src/lj_frame.h	2025-10-09 23:13:59.707792568 +0200
+@@ -155,6 +155,15 @@
+ #define CFRAME_SIZE		(10*8)
+ #define CFRAME_SIZE_JIT		(CFRAME_SIZE + 9*16 + 4*8)
+ #define CFRAME_SHIFT_MULTRES	0
 +#elif LJ_TARGET_LOONGARCH64
 +#define CFRAME_OFS_ERRF		196
 +#define CFRAME_OFS_NRES		192
@@ -5024,13 +5024,13 @@ Index: luajit2-2.1-20250826/src/lj_frame.h
 +#define CFRAME_OFS_MULTRES	0
 +#define CFRAME_SHIFT_MULTRES	3
  #else
- #error "Missing CFRAME_* definitions for this architecture"
- #endif
+ #define CFRAME_OFS_PREV		(4*8)
+ #if LJ_GC64
 Index: luajit2-2.1-20250826/src/lj_gdbjit.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_gdbjit.c
-+++ luajit2-2.1-20250826/src/lj_gdbjit.c
-@@ -309,6 +309,9 @@ enum {
+--- luajit2-2.1-20250826.orig/src/lj_gdbjit.c	2025-10-09 23:13:50.445038431 +0200
++++ luajit2-2.1-20250826/src/lj_gdbjit.c	2025-10-09 23:13:59.707915800 +0200
+@@ -309,6 +309,9 @@
  #elif LJ_TARGET_RISCV64
    DW_REG_SP = 2,
    DW_REG_RA = 1,
@@ -5040,7 +5040,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
  #else
  #error "Unsupported target architecture"
  #endif
-@@ -388,6 +391,8 @@ static const ELFheader elfhdr_template =
+@@ -388,6 +391,8 @@
    .machine = 8,
  #elif LJ_TARGET_RISCV64
    .machine = 243,
@@ -5049,7 +5049,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
  #else
  #error "Unsupported target architecture"
  #endif
-@@ -606,6 +611,13 @@ static void LJ_FASTCALL gdbjit_ehframe(G
+@@ -606,6 +611,13 @@
        DB(DW_CFA_offset|32|9); DUV(29);
        DB(DW_CFA_offset|32|8); DUV(30);
      }
@@ -5065,9 +5065,9 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
  #endif
 Index: luajit2-2.1-20250826/src/lj_jit.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_jit.h
-+++ luajit2-2.1-20250826/src/lj_jit.h
-@@ -108,6 +108,10 @@ struct riscv_hwprobe {
+--- luajit2-2.1-20250826.orig/src/lj_jit.h	2025-10-09 23:13:50.446533754 +0200
++++ luajit2-2.1-20250826/src/lj_jit.h	2025-10-09 23:13:59.708078957 +0200
+@@ -108,6 +108,10 @@
  
  #endif
  
@@ -5078,7 +5078,7 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
  #else
  
  #define JIT_F_CPUSTRING		""
-@@ -409,7 +413,7 @@ enum {
+@@ -409,7 +413,7 @@
    LJ_K64_M2P64_31 = LJ_K64_M2P64,
  #endif
  #endif
@@ -5087,7 +5087,7 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
    LJ_K64_2P31,		/* 2^31 */
  #if LJ_64
    LJ_K64_2P63,		/* 2^63 */
-@@ -418,7 +422,7 @@ enum {
+@@ -418,7 +422,7 @@
  #endif
    LJ_K64__MAX,
  };
@@ -5096,7 +5096,7 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
  
  enum {
  #if LJ_TARGET_X86ORX64
-@@ -428,16 +432,17 @@ enum {
+@@ -428,16 +432,17 @@
    LJ_K32_2P52_2P31,	/* 2^52 + 2^31 */
    LJ_K32_2P52,		/* 2^52 */
  #endif
@@ -5119,9 +5119,9 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
  #define LJ_KSIMD(J, n) \
 Index: luajit2-2.1-20250826/src/lj_target.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_target.h
-+++ luajit2-2.1-20250826/src/lj_target.h
-@@ -55,7 +55,7 @@ typedef uint32_t RegSP;
+--- luajit2-2.1-20250826.orig/src/lj_target.h	2025-10-09 23:13:50.437284165 +0200
++++ luajit2-2.1-20250826/src/lj_target.h	2025-10-09 23:13:59.708231764 +0200
+@@ -55,7 +55,7 @@
  /* Bitset for registers. 32 registers suffice for most architectures.
  ** Note that one set holds bits for both GPRs and FPRs.
  */
@@ -5130,7 +5130,7 @@ Index: luajit2-2.1-20250826/src/lj_target.h
  typedef uint64_t RegSet;
  #define RSET_BITS		6
  #define rset_picktop_(rs)	((Reg)lj_fls64(rs))
-@@ -147,6 +147,8 @@ typedef uint32_t RegCost;
+@@ -147,6 +147,8 @@
  #include "lj_target_s390x.h"
  #elif LJ_TARGET_RISCV64
  #include "lj_target_riscv.h"
@@ -5141,8 +5141,8 @@ Index: luajit2-2.1-20250826/src/lj_target.h
  #endif
 Index: luajit2-2.1-20250826/src/lj_target_loongarch64.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/lj_target_loongarch64.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/lj_target_loongarch64.h	2025-10-09 23:14:02.156250874 +0200
 @@ -0,0 +1,313 @@
 +/*
 +** Definitions for LoongArch CPUs.
@@ -5459,9 +5459,9 @@ Index: luajit2-2.1-20250826/src/lj_target_loongarch64.h
 +
 Index: luajit2-2.1-20250826/src/lj_trace.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_trace.c
-+++ luajit2-2.1-20250826/src/lj_trace.c
-@@ -327,17 +327,17 @@ void lj_trace_initstate(global_State *g)
+--- luajit2-2.1-20250826.orig/src/lj_trace.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_trace.c	2025-10-09 23:13:59.708587403 +0200
+@@ -327,17 +327,17 @@
    J->k64[LJ_K64_2P64].u64 = U64x(43f00000,00000000);
    J->k32[LJ_K32_M2P64_31] = LJ_64 ? 0xdf800000 : 0xcf000000;
  #endif
@@ -5484,9 +5484,9 @@ Index: luajit2-2.1-20250826/src/lj_trace.c
    J->k64[LJ_K64_2P63].u64 = U64x(43e00000,00000000);
 Index: luajit2-2.1-20250826/src/lj_vmmath.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_vmmath.c
-+++ luajit2-2.1-20250826/src/lj_vmmath.c
-@@ -70,7 +70,7 @@ double lj_vm_foldarith(double x, double
+--- luajit2-2.1-20250826.orig/src/lj_vmmath.c	2025-10-09 23:13:50.435766430 +0200
++++ luajit2-2.1-20250826/src/lj_vmmath.c	2025-10-09 23:13:59.708756571 +0200
+@@ -70,7 +70,7 @@
  /* -- Helper functions for generated machine code ------------------------- */
  
  #if (LJ_HASJIT && !(LJ_TARGET_ARM || LJ_TARGET_ARM64 || LJ_TARGET_PPC)) || LJ_TARGET_MIPS \
@@ -5497,8 +5497,8 @@ Index: luajit2-2.1-20250826/src/lj_vmmath.c
    uint32_t y, ua, ub;
 Index: luajit2-2.1-20250826/src/vm_loongarch64.dasc
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/vm_loongarch64.dasc
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/vm_loongarch64.dasc	2025-10-09 23:14:02.156573901 +0200
 @@ -0,0 +1,4625 @@
 +|// Low-level VM code for LoongArch CPUs.
 +|// Bytecode interpreter, fast functions and helper functions.

luajit.changes

@@ -1,14 +1,3 @@
--------------------------------------------------------------------
-Mon Oct 27 14:48:45 UTC 2025 - Andreas Schwab <schwab@suse.de>
-
-- riscv64-support.patch: update from LuaJIT/LuaJIT#1267
-- loong64-support.patch: rediff
-
--------------------------------------------------------------------
-Sun Oct 26 20:16:37 UTC 2025 - Matej Cepl <mcepl@cepl.eu>
-
-- Add Provides: Lua(API)
-
 -------------------------------------------------------------------
 Sat Oct 11 14:16:09 UTC 2025 - Matej Cepl <mcepl@cepl.eu>
 
@@ -19,12 +8,6 @@ Sat Oct 11 14:16:09 UTC 2025 - Matej Cepl <mcepl@cepl.eu>
 Thu Oct  9 21:14:30 UTC 2025 - Matej Cepl <mcepl@cepl.eu>
 
 - Rewrite SPEC file to work with other Lua interpreters and packages.
-- Replace the implementation of LuaJIT of the original
-  implementation of Mike Pall with the OpenResty fork.
-- Just to make rpmlint happy, I have to mention that we removed
-  these patches:
-  - 0003-Get-rid-of-LUAJIT_VERSION_SYM-that-changes-ABI-on-ev.patch
-  - 0002-Enable-debugging-symbols-in-the-build.patch
 - Reapply patches to avoid fuzz and long-term maintenance:
   - loong64-support.patch
   - riscv64-support.patch

luajit.spec

@@ -35,7 +35,7 @@ URL:            https://github.com/openresty/%{name}
 
 Source0:        https://github.com/openresty/luajit2/archive/refs/tags/v%{major}-%{minor}.tar.gz#/luajit2-%{major}-%{minor}.tar.gz
 Source1:        baselibs.conf
-# https://patch-diff.githubusercontent.com/raw/openresty/luajit2/pull/236.patch#/riscv64-support.patch
+# https://patch-diff.githubusercontent.com/raw/openresty/luajit2/pull/236.patch#/riscv64-support.patch#/riscv64-support.patch
 Patch0:         riscv64-support.patch
 # https://github.com/openresty/luajit2/pull/245/commits/8e40aca7b3a919456b15698273e9b00e9250e769.patch#/loong64-support.patch
 Patch1:         loong64-support.patch
@@ -47,7 +47,6 @@ Obsoletes:      lua51-luajit < %{version}
 Provides:       moonjit = %{version}-%{release}
 Obsoletes:      moonjit < %{version}
 Provides:       lua = %{version}-%{release}
-Provides:       Lua(API) = %{major}
 # lj_arch.h:441:2: error: #error "No target architecture defined"
 # ExclusiveArch:  x86_64 %%{ix86} aarch64 %%{arm} ppc mips mips64 mips64el s390x
 # Both lua51 and luajit use %%{_libdir}/lua/%%{abi_ver}

riscv64-support.patch

@@ -1,45 +1,45 @@
-From 2578bb041ee4a50f636b00287860f1dd7e7ce860 Mon Sep 17 00:00:00 2001
+From f97b378df83699f05cb34b463f3add4ce70e06a0 Mon Sep 17 00:00:00 2001
 From: gns <infiwang@proton.me>
 Date: Tue, 5 Mar 2024 17:09:31 +0800
 Subject: [PATCH 01/22] riscv(support): add RISC-V 64 arch base definition
 
 ---
- Makefile                |    1 +
- dynasm/dasm_riscv.h     |  433 +++++
- dynasm/dasm_riscv.lua   |  979 ++++++++++
- dynasm/dasm_riscv32.lua |   12 +
- dynasm/dasm_riscv64.lua |   12 +
- src/Makefile            |    8 +
- src/host/buildvm.c      |    2 +
- src/host/buildvm_asm.c  |   31 +
- src/jit/bcsave.lua      |    1 +
- src/jit/dis_riscv.lua   |  979 ++++++++++
- src/jit/dis_riscv64.lua |   16 +
- src/lib_jit.c           |  121 ++
- src/lj_alloc.c          |    2 +-
- src/lj_arch.h           |   23 +
- src/lj_asm.c            |    4 +
+ Makefile                |    1 
+ dynasm/dasm_riscv.h     |  435 ++++
+ dynasm/dasm_riscv.lua   |  979 +++++++++
+ dynasm/dasm_riscv32.lua |   12 
+ dynasm/dasm_riscv64.lua |   12 
+ src/Makefile            |    8 
+ src/host/buildvm.c      |    2 
+ src/host/buildvm_asm.c  |   31 
+ src/jit/bcsave.lua      |    1 
+ src/jit/dis_riscv.lua   |  979 +++++++++
+ src/jit/dis_riscv64.lua |   16 
+ src/lib_jit.c           |  121 +
+ src/lj_alloc.c          |    2 
+ src/lj_arch.h           |   22 
+ src/lj_asm.c            |    4 
  src/lj_asm_riscv64.h    | 2037 ++++++++++++++++++++
- src/lj_ccall.c          |  156 +-
- src/lj_ccall.h          |   17 +-
- src/lj_ccallback.c      |   64 +-
- src/lj_emit_riscv.h     |  574 ++++++
- src/lj_frame.h          |    9 +
- src/lj_gdbjit.c         |   15 +
- src/lj_jit.h            |   40 +
- src/lj_mcode.c          |   17 +
- src/lj_target.h         |    4 +-
- src/lj_target_riscv.h   |  542 ++++++
- src/lj_vm.h             |    3 +
- src/lj_vmmath.c         |    3 +-
- src/vm_riscv64.dasc     | 4813 +++++++++++++++++++++++++++++++++++++++++++++++
- 29 files changed, 10911 insertions(+), 7 deletions(-)
+ src/lj_ccall.c          |  156 +
+ src/lj_ccall.h          |   17 
+ src/lj_ccallback.c      |   64 
+ src/lj_emit_riscv.h     |  574 +++++
+ src/lj_frame.h          |    9 
+ src/lj_gdbjit.c         |   15 
+ src/lj_jit.h            |   40 
+ src/lj_mcode.c          |   17 
+ src/lj_target.h         |    4 
+ src/lj_target_riscv.h   |  542 +++++
+ src/lj_vm.h             |    3 
+ src/lj_vmmath.c         |    3 
+ src/vm_riscv64.dasc     | 4813 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 29 files changed, 10912 insertions(+), 7 deletions(-)
 
 Index: luajit2-2.1-20250826/Makefile
 ===================================================================
---- luajit2-2.1-20250826.orig/Makefile
-+++ luajit2-2.1-20250826/Makefile
-@@ -101,6 +101,7 @@ FILES_JITLIB= bc.lua bcsave.lua dump.lua
+--- luajit2-2.1-20250826.orig/Makefile	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/Makefile	2025-10-09 23:13:50.446088447 +0200
+@@ -101,6 +101,7 @@
  	      dis_arm64be.lua dis_ppc.lua dis_mips.lua dis_mipsel.lua \
  	      dis_mips64.lua dis_mips64el.lua \
  	      dis_mips64r6.lua dis_mips64r6el.lua \
@@ -49,13 +49,15 @@ Index: luajit2-2.1-20250826/Makefile
  ifeq (,$(findstring Windows,$(OS)))
 Index: luajit2-2.1-20250826/dynasm/dasm_riscv.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/dynasm/dasm_riscv.h
-@@ -0,0 +1,433 @@
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/dynasm/dasm_riscv.h	2025-10-09 23:13:50.433358410 +0200
+@@ -0,0 +1,435 @@
 +/*
 +** DynASM RISC-V encoding engine.
 +** Copyright (C) 2005-2025 Mike Pall. All rights reserved.
 +** Released under the MIT license. See dynasm.lua for full copyright notice.
++**
++** Contributed by gns from PLCT Lab, ISCAS.
 +*/
 +
 +#include <stddef.h>
@@ -487,8 +489,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv.h
 +
 Index: luajit2-2.1-20250826/dynasm/dasm_riscv.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/dynasm/dasm_riscv.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/dynasm/dasm_riscv.lua	2025-10-09 23:13:53.940825099 +0200
 @@ -0,0 +1,979 @@
 +------------------------------------------------------------------------------
 +-- DynASM RISC-V module.
@@ -918,7 +920,7 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv.lua
 +  -- RV32D
 +  ["fld_2"] = "00003007FL",
 +  ["fsd_2"] = "00003027gS",
-+  
++
 +  ["fmadd.d_4"]  = "02000043FGgH",
 +  ["fmsub.d_4"]  = "02000047FGgH",
 +  ["fnmsub.d_4"] = "0200004bFGgH",
@@ -1471,8 +1473,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv.lua
 +
 Index: luajit2-2.1-20250826/dynasm/dasm_riscv32.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/dynasm/dasm_riscv32.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/dynasm/dasm_riscv32.lua	2025-10-09 23:13:50.434338754 +0200
 @@ -0,0 +1,12 @@
 +------------------------------------------------------------------------------
 +-- DynASM RISC-V 32 module.
@@ -1488,8 +1490,8 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv32.lua
 +return require("dasm_riscv")
 Index: luajit2-2.1-20250826/dynasm/dasm_riscv64.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/dynasm/dasm_riscv64.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/dynasm/dasm_riscv64.lua	2025-10-09 23:13:50.434521368 +0200
 @@ -0,0 +1,12 @@
 +------------------------------------------------------------------------------
 +-- DynASM RISC-V 64 module.
@@ -1505,9 +1507,9 @@ Index: luajit2-2.1-20250826/dynasm/dasm_riscv64.lua
 +return require("dasm_riscv")
 Index: luajit2-2.1-20250826/src/Makefile
 ===================================================================
---- luajit2-2.1-20250826.orig/src/Makefile
-+++ luajit2-2.1-20250826/src/Makefile
-@@ -52,6 +52,7 @@ CCOPT_arm=
+--- luajit2-2.1-20250826.orig/src/Makefile	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/Makefile	2025-10-09 23:13:50.446195839 +0200
+@@ -52,6 +52,7 @@
  CCOPT_arm64=
  CCOPT_ppc=
  CCOPT_mips=
@@ -1515,7 +1517,7 @@ Index: luajit2-2.1-20250826/src/Makefile
  #
  #CCDEBUG=
  # Uncomment the next line to generate debug information:
-@@ -270,6 +271,9 @@ ifneq (,$(findstring LJ_TARGET_MIPS ,$(T
+@@ -270,6 +271,9 @@
      TARGET_LJARCH= mips
    endif
  else
@@ -1525,7 +1527,7 @@ Index: luajit2-2.1-20250826/src/Makefile
    $(error Unsupported target architecture)
  endif
  endif
-@@ -278,6 +282,7 @@ endif
+@@ -278,6 +282,7 @@
  endif
  endif
  endif
@@ -1533,7 +1535,7 @@ Index: luajit2-2.1-20250826/src/Makefile
  
  ifneq (,$(findstring LJ_TARGET_PS3 1,$(TARGET_TESTARCH)))
    TARGET_SYS= PS3
-@@ -487,6 +492,9 @@ ifeq (ppc,$(TARGET_LJARCH))
+@@ -487,6 +492,9 @@
      DASM_AFLAGS+= -D ELFV2
    endif
  endif
@@ -1545,9 +1547,9 @@ Index: luajit2-2.1-20250826/src/Makefile
  
 Index: luajit2-2.1-20250826/src/host/buildvm.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/host/buildvm.c
-+++ luajit2-2.1-20250826/src/host/buildvm.c
-@@ -69,6 +69,8 @@ static int collect_reloc(BuildCtx *ctx,
+--- luajit2-2.1-20250826.orig/src/host/buildvm.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/host/buildvm.c	2025-10-09 23:13:50.441017227 +0200
+@@ -69,6 +69,8 @@
  #include "../dynasm/dasm_mips.h"
  #elif LJ_TARGET_S390X
  #include "../dynasm/dasm_s390x.h"
@@ -1558,9 +1560,9 @@ Index: luajit2-2.1-20250826/src/host/buildvm.c
  #endif
 Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c
-+++ luajit2-2.1-20250826/src/host/buildvm_asm.c
-@@ -208,6 +208,34 @@ static void emit_asm_wordreloc(BuildCtx
+--- luajit2-2.1-20250826.orig/src/host/buildvm_asm.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/host/buildvm_asm.c	2025-10-09 23:13:50.441145889 +0200
+@@ -208,6 +208,34 @@
  	  "Error: unsupported opcode %08x for %s symbol relocation.\n",
  	  ins, sym);
    exit(1);
@@ -1595,32 +1597,32 @@ Index: luajit2-2.1-20250826/src/host/buildvm_asm.c
  #else
  #error "missing relocation support for this architecture"
  #endif
-@@ -304,6 +332,9 @@ void emit_asm(BuildCtx *ctx)
+@@ -304,6 +332,9 @@
  #if LJ_TARGET_MIPS
    fprintf(ctx->fp, "\t.set nomips16\n\t.abicalls\n\t.set noreorder\n\t.set nomacro\n");
  #endif
 +#if LJ_TARGET_RISCV64
-+  fprintf(ctx->fp, ".option norvc\n.option norelax\n");
++  fprintf(ctx->fp, ".option arch, -c\n.option norelax\n");
 +#endif
    emit_asm_align(ctx, 4);
  
  #if LJ_TARGET_PS3
 Index: luajit2-2.1-20250826/src/jit/bcsave.lua
 ===================================================================
---- luajit2-2.1-20250826.orig/src/jit/bcsave.lua
-+++ luajit2-2.1-20250826/src/jit/bcsave.lua
-@@ -103,6 +103,7 @@ local map_arch = {
+--- luajit2-2.1-20250826.orig/src/jit/bcsave.lua	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/jit/bcsave.lua	2025-10-09 23:13:50.441296523 +0200
+@@ -103,6 +103,7 @@
    mips64r6 =	{ e = "be", b = 64, m = 8, f = 0xa0000407, },
    mips64r6el =	{ e = "le", b = 64, m = 8, f = 0xa0000407, },
    s390x =	{ e = "be", b = 64, m = 22, },
-+  riscv64 =     { e = "le", b = 64, m = 243, f = 0x00000004, },
++  riscv64 =    { e = "le", b = 64, m = 243, f = 0x00000004, },
  }
  
  local map_os = {
 Index: luajit2-2.1-20250826/src/jit/dis_riscv.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/jit/dis_riscv.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/jit/dis_riscv.lua	2025-10-09 23:13:50.445749188 +0200
 @@ -0,0 +1,979 @@
 +------------------------------------------------------------------------------
 +-- LuaJIT RISC-V disassembler module.
@@ -2603,8 +2605,8 @@ Index: luajit2-2.1-20250826/src/jit/dis_riscv.lua
 +}
 Index: luajit2-2.1-20250826/src/jit/dis_riscv64.lua
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/jit/dis_riscv64.lua
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/jit/dis_riscv64.lua	2025-10-09 23:13:50.445924448 +0200
 @@ -0,0 +1,16 @@
 +----------------------------------------------------------------------------
 +-- LuaJIT RISC-V 64 disassembler wrapper module.
@@ -2625,9 +2627,9 @@ Index: luajit2-2.1-20250826/src/jit/dis_riscv64.lua
 \ No newline at end of file
 Index: luajit2-2.1-20250826/src/lib_jit.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lib_jit.c
-+++ luajit2-2.1-20250826/src/lib_jit.c
-@@ -697,6 +697,104 @@ JIT_PARAMDEF(JIT_PARAMINIT)
+--- luajit2-2.1-20250826.orig/src/lib_jit.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lib_jit.c	2025-10-09 23:13:50.446361090 +0200
+@@ -697,6 +697,104 @@
  #include <sys/utsname.h>
  #endif
  
@@ -2732,7 +2734,7 @@ Index: luajit2-2.1-20250826/src/lib_jit.c
  /* Arch-dependent CPU feature detection. */
  static uint32_t jit_cpudetect(void)
  {
-@@ -769,6 +867,29 @@ static uint32_t jit_cpudetect(void)
+@@ -769,6 +867,29 @@
  #endif
  #elif LJ_TARGET_S390X
    /* No optional CPU features to detect (for now). */
@@ -2764,9 +2766,9 @@ Index: luajit2-2.1-20250826/src/lib_jit.c
  #endif
 Index: luajit2-2.1-20250826/src/lj_alloc.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_alloc.c
-+++ luajit2-2.1-20250826/src/lj_alloc.c
-@@ -365,7 +365,7 @@ static void *CALL_MREMAP_(void *ptr, siz
+--- luajit2-2.1-20250826.orig/src/lj_alloc.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_alloc.c	2025-10-09 23:13:50.445417785 +0200
+@@ -365,7 +365,7 @@
  #define CALL_MREMAP(addr, osz, nsz, mv) CALL_MREMAP_((addr), (osz), (nsz), (mv))
  #define CALL_MREMAP_NOMOVE	0
  #define CALL_MREMAP_MAYMOVE	1
@@ -2777,14 +2779,14 @@ Index: luajit2-2.1-20250826/src/lj_alloc.c
  #define CALL_MREMAP_MV		CALL_MREMAP_MAYMOVE
 Index: luajit2-2.1-20250826/src/lj_arch.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_arch.h
-+++ luajit2-2.1-20250826/src/lj_arch.h
+--- luajit2-2.1-20250826.orig/src/lj_arch.h	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_arch.h	2025-10-09 23:13:50.433083022 +0200
 @@ -33,6 +33,8 @@
  #define LUAJIT_ARCH_mips64	7
  #define LUAJIT_ARCH_S390X	8
  #define LUAJIT_ARCH_s390x	8
-+#define LUAJIT_ARCH_riscv64	9
 +#define LUAJIT_ARCH_RISCV64	9
++#define LUAJIT_ARCH_riscv64	9
  
  /* Target OS. */
  #define LUAJIT_OS_OTHER		0
@@ -2797,10 +2799,10 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
  #else
  #error "Architecture not supported (in this version), see: https://luajit.org/status.html#architectures"
  #endif
-@@ -471,6 +475,21 @@
+@@ -470,6 +474,20 @@
+ #define LJ_ARCH_NUMMODE		LJ_NUMMODE_DUAL
  #define LJ_TARGET_GC64		1
  #define LJ_ARCH_NOJIT		1	/* NYI */
- 
 +#elif LUAJIT_TARGET == LUAJIT_ARCH_RISCV64
 +
 +#define LJ_ARCH_NAME		"riscv64"
@@ -2815,11 +2817,10 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
 +#define LJ_TARGET_MASKSHIFT	1
 +#define LJ_TARGET_MASKROT	1
 +#define LJ_ARCH_NUMMODE		LJ_NUMMODE_DUAL
-+
+ 
  #else
  #error "No target architecture defined"
- #endif
-@@ -554,6 +573,10 @@
+@@ -554,6 +572,10 @@
  #error "Only n64 ABI supported for MIPS64"
  #undef LJ_TARGET_MIPS
  #endif
@@ -2832,9 +2833,9 @@ Index: luajit2-2.1-20250826/src/lj_arch.h
  
 Index: luajit2-2.1-20250826/src/lj_asm.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_asm.c
-+++ luajit2-2.1-20250826/src/lj_asm.c
-@@ -227,6 +227,8 @@ static Reg rset_pickrandom(ASMState *as,
+--- luajit2-2.1-20250826.orig/src/lj_asm.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_asm.c	2025-10-09 23:13:50.439989544 +0200
+@@ -227,6 +227,8 @@
  #include "lj_emit_ppc.h"
  #elif LJ_TARGET_MIPS
  #include "lj_emit_mips.h"
@@ -2843,7 +2844,7 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
  #else
  #error "Missing instruction emitter for target CPU"
  #endif
-@@ -1710,6 +1712,8 @@ static void asm_loop(ASMState *as)
+@@ -1710,6 +1712,8 @@
  #include "lj_asm_mips.h"
  #elif LJ_TARGET_S390X
  #include "lj_asm_s390x.h"
@@ -2854,8 +2855,8 @@ Index: luajit2-2.1-20250826/src/lj_asm.c
  #endif
 Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/lj_asm_riscv64.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/lj_asm_riscv64.h	2025-10-09 23:13:53.941477235 +0200
 @@ -0,0 +1,2037 @@
 +/*
 +** RISC-V IR assembler (SSA IR -> machine code).
@@ -3553,7 +3554,7 @@ Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
 +      key = ra_alloc1(as, refkey, allow);
 +      rset_clear(allow, key);
 +    }
-+  } 
++  }
 +
 +  /* Key not found in chain: jump to exit (if merged) or load niltv. */
 +  l_end = emit_label(as);
@@ -4105,11 +4106,11 @@ Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
 +    emit_ds(as, RISCVI_FCVT_D_L, ftmp, RID_TMP);
 +  }
 +  emit_ds(as, riscvi, RID_TMP, left);
-+  emit_branch(as, RISCVI_BLT, RID_ZERO, RID_TMP, l_end, -1);
++  emit_branch(as, RISCVI_BLT, RID_ZERO, RID_TMP, l_end, 0);
 +  emit_dsi(as, RISCVI_ADDI, RID_TMP, RID_TMP, -1075);
 +  emit_dsi(as, RISCVI_ANDI, RID_TMP, RID_TMP, 0x7ff);
 +  emit_dsi(as, RISCVI_SRLI, RID_TMP, RID_TMP, 52);
-+  if (dest != left) 
++  if (dest != left)
 +    emit_ds1s2(as, RISCVI_FMV_D, dest, left, left);
 +  emit_ds(as, RISCVI_FMV_X_D, RID_TMP, left);
 +}
@@ -4896,8 +4897,8 @@ Index: luajit2-2.1-20250826/src/lj_asm_riscv64.h
 +}
 Index: luajit2-2.1-20250826/src/lj_ccall.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_ccall.c
-+++ luajit2-2.1-20250826/src/lj_ccall.c
+--- luajit2-2.1-20250826.orig/src/lj_ccall.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_ccall.c	2025-10-09 23:13:50.437724513 +0200
 @@ -687,6 +687,97 @@
      if (ngpr < maxgpr) { dp = &cc->gpr[ngpr++]; goto done; } \
    }
@@ -4996,7 +4997,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
  #else
  #error "Missing calling convention definitions for this architecture"
  #endif
-@@ -1055,6 +1146,51 @@ static void ccall_copy_struct(CCallState
+@@ -1055,6 +1146,51 @@
  
  #endif
  
@@ -5048,7 +5049,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
  /* -- Common C call handling ---------------------------------------------- */
  
  /* Infer the destination CTypeID for a vararg argument.
-@@ -1106,6 +1242,10 @@ static int ccall_set_args(lua_State *L,
+@@ -1106,6 +1242,10 @@
  #endif
  #endif
  
@@ -5059,7 +5060,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
    /* Clear unused regs to get some determinism in case of misdeclaration. */
    memset(cc->gpr, 0, sizeof(cc->gpr));
  #if CCALL_NUM_FPR
-@@ -1295,7 +1435,11 @@ static int ccall_set_args(lua_State *L,
+@@ -1295,7 +1435,11 @@
          *(int64_t *)dp = (int64_t)*(int32_t *)dp;
      }
  #endif
@@ -5072,7 +5073,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
      if ((ctype_isinteger_or_bool(d->info) || ctype_isenum(d->info)
  #if LJ_TARGET_MIPS64
  	 || (isfp && nsp == 0)
-@@ -1335,6 +1479,14 @@ static int ccall_set_args(lua_State *L,
+@@ -1335,6 +1479,14 @@
        CTSize i = (sz >> 2) - 1;
        do { ((uint64_t *)dp)[i] = ((uint32_t *)dp)[i]; } while (i--);
      }
@@ -5087,7 +5088,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
  #else
      UNUSED(isfp);
  #endif
-@@ -1344,7 +1496,7 @@ static int ccall_set_args(lua_State *L,
+@@ -1344,7 +1496,7 @@
    if ((int32_t)nsp < 0) nsp = 0;
  #endif
  
@@ -5098,9 +5099,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.c
    cc->nsp = (nsp + CTSIZE_PTR-1) & ~(CTSIZE_PTR-1);
 Index: luajit2-2.1-20250826/src/lj_ccall.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_ccall.h
-+++ luajit2-2.1-20250826/src/lj_ccall.h
-@@ -157,6 +157,21 @@ typedef union FPRArg {
+--- luajit2-2.1-20250826.orig/src/lj_ccall.h	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_ccall.h	2025-10-09 23:13:50.437992427 +0200
+@@ -157,6 +157,21 @@
    float f;
  } FPRArg;
  
@@ -5122,7 +5123,7 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
  #else
  #error "Missing calling convention definitions for this architecture"
  #endif
-@@ -204,7 +219,7 @@ typedef LJ_ALIGN(CCALL_ALIGN_CALLSTATE)
+@@ -204,7 +219,7 @@
    uint8_t resx87;		/* Result on x87 stack: 1:float, 2:double. */
  #elif LJ_TARGET_ARM64
    void *retp;			/* Aggregate return pointer in x8. */
@@ -5133,9 +5134,9 @@ Index: luajit2-2.1-20250826/src/lj_ccall.h
  #if LJ_32
 Index: luajit2-2.1-20250826/src/lj_ccallback.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_ccallback.c
-+++ luajit2-2.1-20250826/src/lj_ccallback.c
-@@ -91,6 +91,10 @@ static MSize CALLBACK_OFS2SLOT(MSize ofs
+--- luajit2-2.1-20250826.orig/src/lj_ccallback.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_ccallback.c	2025-10-09 23:13:50.438123303 +0200
+@@ -91,6 +91,10 @@
  
  #define CALLBACK_MCODE_HEAD		52
  
@@ -5146,7 +5147,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  #else
  
  /* Missing support for this architecture. */
-@@ -293,6 +297,39 @@ static void *callback_mcode_init(global_
+@@ -293,6 +297,39 @@
    }
    return p;
  }
@@ -5186,7 +5187,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  #else
  /* Missing support for this architecture. */
  #define callback_mcode_init(g, p)	(p)
-@@ -595,6 +632,31 @@ void lj_ccallback_mcode_free(CTState *ct
+@@ -595,6 +632,31 @@
      if (ngpr < maxgpr) { sp = &cts->cb.gpr[ngpr++]; goto done; } \
    }
  
@@ -5218,7 +5219,7 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  #else
  #error "Missing calling convention definitions for this architecture"
  #endif
-@@ -750,7 +812,7 @@ static void callback_conv_result(CTState
+@@ -750,7 +812,7 @@
          *(int64_t *)dp = (int64_t)*(int32_t *)dp;
      }
  #endif
@@ -5229,8 +5230,8 @@ Index: luajit2-2.1-20250826/src/lj_ccallback.c
  	(LJ_ABI_SOFTFP || ctype_isinteger_or_bool(ctr->info)))
 Index: luajit2-2.1-20250826/src/lj_emit_riscv.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/lj_emit_riscv.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/lj_emit_riscv.h	2025-10-09 23:13:53.942748326 +0200
 @@ -0,0 +1,574 @@
 +/*
 +** RISC-V instruction emitter.
@@ -5460,7 +5461,7 @@ Index: luajit2-2.1-20250826/src/lj_emit_riscv.h
 +        lj_assertA(0, "invalid ext op");
 +        return;
 +    }
-+    emit_dsshamt(as, sri, rd, rd, shamt);   
++    emit_dsshamt(as, sri, rd, rd, shamt);
 +    emit_dsshamt(as, sli, rd, rs1, shamt);
 +  }
 +}
@@ -5808,9 +5809,9 @@ Index: luajit2-2.1-20250826/src/lj_emit_riscv.h
 +#define emit_spsub(as, ofs)	emit_addptr(as, RID_SP, -(ofs))
 Index: luajit2-2.1-20250826/src/lj_frame.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_frame.h
-+++ luajit2-2.1-20250826/src/lj_frame.h
-@@ -287,6 +287,15 @@ enum { LJ_CONT_TAILCALL, LJ_CONT_FFI_CAL
+--- luajit2-2.1-20250826.orig/src/lj_frame.h	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_frame.h	2025-10-09 23:13:50.434938112 +0200
+@@ -287,6 +287,15 @@
  ** need to change to 3.
  */
  #define CFRAME_SHIFT_MULTRES	0
@@ -5828,9 +5829,9 @@ Index: luajit2-2.1-20250826/src/lj_frame.h
  #endif
 Index: luajit2-2.1-20250826/src/lj_gdbjit.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_gdbjit.c
-+++ luajit2-2.1-20250826/src/lj_gdbjit.c
-@@ -306,6 +306,9 @@ enum {
+--- luajit2-2.1-20250826.orig/src/lj_gdbjit.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_gdbjit.c	2025-10-09 23:13:50.445038431 +0200
+@@ -306,6 +306,9 @@
  #elif LJ_TARGET_MIPS
    DW_REG_SP = 29,
    DW_REG_RA = 31,
@@ -5840,7 +5841,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
  #else
  #error "Unsupported target architecture"
  #endif
-@@ -383,6 +386,8 @@ static const ELFheader elfhdr_template =
+@@ -383,6 +386,8 @@
    .machine = 20,
  #elif LJ_TARGET_MIPS
    .machine = 8,
@@ -5849,7 +5850,7 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
  #else
  #error "Unsupported target architecture"
  #endif
-@@ -591,6 +596,16 @@ static void LJ_FASTCALL gdbjit_ehframe(G
+@@ -591,6 +596,16 @@
        for (i = 23; i >= 16; i--) { DB(DW_CFA_offset|i); DUV(26-i); }
        for (i = 30; i >= 20; i -= 2) { DB(DW_CFA_offset|32|i); DUV(42-i); }
      }
@@ -5868,8 +5869,8 @@ Index: luajit2-2.1-20250826/src/lj_gdbjit.c
  #endif
 Index: luajit2-2.1-20250826/src/lj_jit.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_jit.h
-+++ luajit2-2.1-20250826/src/lj_jit.h
+--- luajit2-2.1-20250826.orig/src/lj_jit.h	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_jit.h	2025-10-09 23:13:50.446533754 +0200
 @@ -68,6 +68,46 @@
  #endif
  #endif
@@ -5919,8 +5920,8 @@ Index: luajit2-2.1-20250826/src/lj_jit.h
  #define JIT_F_CPUSTRING		""
 Index: luajit2-2.1-20250826/src/lj_mcode.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_mcode.c
-+++ luajit2-2.1-20250826/src/lj_mcode.c
+--- luajit2-2.1-20250826.orig/src/lj_mcode.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_mcode.c	2025-10-09 23:13:50.445281779 +0200
 @@ -38,6 +38,12 @@
  void sys_icache_invalidate(void *start, size_t len);
  #endif
@@ -5934,7 +5935,7 @@ Index: luajit2-2.1-20250826/src/lj_mcode.c
  /* Synchronize data/instruction cache. */
  void lj_mcode_sync(void *start, void *end)
  {
-@@ -52,6 +58,17 @@ void lj_mcode_sync(void *start, void *en
+@@ -52,6 +58,17 @@
    sys_icache_invalidate(start, (char *)end-(char *)start);
  #elif LJ_TARGET_PPC
    lj_vm_cachesync(start, end);
@@ -5954,9 +5955,9 @@ Index: luajit2-2.1-20250826/src/lj_mcode.c
  #else
 Index: luajit2-2.1-20250826/src/lj_target.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_target.h
-+++ luajit2-2.1-20250826/src/lj_target.h
-@@ -55,7 +55,7 @@ typedef uint32_t RegSP;
+--- luajit2-2.1-20250826.orig/src/lj_target.h	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_target.h	2025-10-09 23:13:50.437284165 +0200
+@@ -55,7 +55,7 @@
  /* Bitset for registers. 32 registers suffice for most architectures.
  ** Note that one set holds bits for both GPRs and FPRs.
  */
@@ -5965,7 +5966,7 @@ Index: luajit2-2.1-20250826/src/lj_target.h
  typedef uint64_t RegSet;
  #define RSET_BITS		6
  #define rset_picktop_(rs)	((Reg)lj_fls64(rs))
-@@ -145,6 +145,8 @@ typedef uint32_t RegCost;
+@@ -145,6 +145,8 @@
  #include "lj_target_mips.h"
  #elif LJ_TARGET_S390X
  #include "lj_target_s390x.h"
@@ -5976,8 +5977,8 @@ Index: luajit2-2.1-20250826/src/lj_target.h
  #endif
 Index: luajit2-2.1-20250826/src/lj_target_riscv.h
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/lj_target_riscv.h
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/lj_target_riscv.h	2025-10-09 23:13:50.437461959 +0200
 @@ -0,0 +1,542 @@
 +/*
 +** Definitions for RISC-V CPUs.
@@ -6523,9 +6524,9 @@ Index: luajit2-2.1-20250826/src/lj_target_riscv.h
 +#endif
 Index: luajit2-2.1-20250826/src/lj_vm.h
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_vm.h
-+++ luajit2-2.1-20250826/src/lj_vm.h
-@@ -37,6 +37,9 @@ LJ_ASMF int lj_vm_cpuid(uint32_t f, uint
+--- luajit2-2.1-20250826.orig/src/lj_vm.h	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_vm.h	2025-10-09 23:13:50.435674046 +0200
+@@ -37,6 +37,9 @@
  #if LJ_TARGET_PPC
  void lj_vm_cachesync(void *start, void *end);
  #endif
@@ -6537,9 +6538,9 @@ Index: luajit2-2.1-20250826/src/lj_vm.h
  LJ_ASMF double lj_vm_foldfpm(double x, int op);
 Index: luajit2-2.1-20250826/src/lj_vmmath.c
 ===================================================================
---- luajit2-2.1-20250826.orig/src/lj_vmmath.c
-+++ luajit2-2.1-20250826/src/lj_vmmath.c
-@@ -69,7 +69,8 @@ double lj_vm_foldarith(double x, double
+--- luajit2-2.1-20250826.orig/src/lj_vmmath.c	2025-08-26 14:24:06.000000000 +0200
++++ luajit2-2.1-20250826/src/lj_vmmath.c	2025-10-09 23:13:50.435766430 +0200
+@@ -69,7 +69,8 @@
  
  /* -- Helper functions for generated machine code ------------------------- */
  
@@ -6551,15 +6552,14 @@ Index: luajit2-2.1-20250826/src/lj_vmmath.c
    uint32_t y, ua, ub;
 Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 ===================================================================
---- /dev/null
-+++ luajit2-2.1-20250826/src/vm_riscv64.dasc
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ luajit2-2.1-20250826/src/vm_riscv64.dasc	2025-10-09 23:13:53.943164149 +0200
 @@ -0,0 +1,4813 @@
 +|// Low-level VM code for RISC-V 64 CPUs.
 +|// Bytecode interpreter, fast functions and helper functions.
 +|// Copyright (C) 2005-2025 Mike Pall. See Copyright Notice in luajit.h
 +|//
 +|// Contributed by gns from PLCT Lab, ISCAS.
-+|// Sponsored by PLCT Lab, ISCAS.
 +|
 +|.arch riscv64
 +|.section code_op, code_sub
@@ -7623,7 +7623,7 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +  |->vmeta_istype:
 +  |  addi PC, PC, -4
 +  |   sd BASE, L->base
-+  |   mv CARG1, L 
++  |   mv CARG1, L
 +  |   srliw CARG2, RA, 3
 +  |   srliw CARG3, RD, 3
 +  |  sd PC, SAVE_PC(sp)
@@ -9590,13 +9590,14 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +    |  // RA = dst*8 or unused, RD = src*8, JMP with RD = target
 +    |  add RD, BASE, RD
 +    |   lhu TMP2, OFS_RD(PC)
-+    |  ld CRET1, 0(RD)
++    |  ld TMP0, 0(RD)
 +    |   addi PC, PC, 4
-+    |  gettp TMP0, CRET1
++    |  gettp TMP0, TMP0
 +    |  add RA, BASE, RA
 +    |  sltiu TMP0, TMP0, LJ_TISTRUECOND		// TMP0=1 true; TMP0=0 false
 +    |  decode_BC4b TMP2
 +    |  lui TMP3, (-(BCBIAS_J*4 >> 12)) & 0xfffff		// -BCBIAS_J*4
++    |  ld CRET1, 0(RD)
 +    |  addw TMP2, TMP2, TMP3		// (jump-0x8000)<<2
 +    if (op == BC_IST || op == BC_ISTC) {
 +      |  beqz TMP0, >1
@@ -9666,9 +9667,8 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +    |  lui TMP1, 0x80000
 +    |  gettp CARG3, TMP0
 +    |  bne CARG3, TISNUM, >1
-+    |  sext.w TMP0, TMP0
-+    |  bxeq TMP0, TMP1, ->vmeta_unm      // Meta handler deals with -2^31.
 +    |  negw TMP0, TMP0
++    |  bxeq TMP0, TMP1, ->vmeta_unm      // Meta handler deals with -2^31.
 +    |  zext.w TMP0, TMP0
 +    |  settp_b TMP0, TISNUM
 +    |  j >2
@@ -9767,7 +9767,7 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +    |  ins_next2
 +    |.endmacro
 +    |
-+    |.macro ins_arithead, itype1, itype2, tval1, tval2 
++    |.macro ins_arithead, itype1, itype2, tval1, tval2
 +    |  ld tval1, 0(RB)
 +    |  ld tval2, 0(RC)
 +    |  // Check for two integers.
@@ -9833,7 +9833,7 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +    |1:  // Check for two numbers.
 +    |  ins_arithfp, fpins, TMP0, TMP1
 +    |.endmacro
-+    
++
 +  case BC_ADDVN: case BC_ADDNV: case BC_ADDVV:
 +    |  ins_arithdn addw, fadd.d
 +    break;
@@ -10380,9 +10380,9 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +    |    ld TAB:TMP0, TAB:RB->metatable
 +    |   beq CARG2, TISNIL, >4		// Key found, but nil value?
 +    |2:
-+    |  andi TMP4, TMP3, LJ_GC_BLACK	// isblack(table)
++    |  andi TMP3, TMP3, LJ_GC_BLACK	// isblack(table)
 +    |   fsd FTMP0, NODE:TMP2->val
-+    |  bnez TMP4, >7
++    |  bnez TMP3, >7
 +    |3:
 +    |  ins_next
 +    |
@@ -10555,10 +10555,11 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +  case BC_CALLMT:
 +    |  // RA = base*8, (RB = 0,) RC = extra_nargs*8
 +    |  addw NARGS8:RD, NARGS8:RD, MULTRES
-+    |  // Fall through. Assumes BC_CALLT follows.
++    |  j ->BC_CALLT_Z1
 +    break;
 +  case BC_CALLT:
 +    |  // RA = base*8, (RB = 0,) RC = (nargs+1)*8
++    |->BC_CALLT_Z1:
 +    |  add RA, BASE, RA
 +    |  ld LFUNC:RB, 0(RA)
 +    |   mv NARGS8:RC, RD
@@ -10804,11 +10805,12 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +  case BC_RETM:
 +    |  // RA = results*8, RD = extra_nresults*8
 +    |  addw RD, RD, MULTRES
-+    |  // Fall through. Assumes BC_RET follows.
++    |  j ->BC_RET_Z1
 +    break;
 +
 +  case BC_RET:
 +    |  // RA = results*8, RD = (nresults+1)*8
++    |->BC_RET_Z1:
 +    |  ld PC, FRAME_PC(BASE)
 +    |   add RA, BASE, RA
 +    |    mv MULTRES, RD
@@ -10841,9 +10843,8 @@ Index: luajit2-2.1-20250826/src/vm_riscv64.dasc
 +    |   ld LFUNC:TMP1, FRAME_FUNC(BASE)
 +    |  cleartp LFUNC:TMP1
 +    |  ld TMP1, LFUNC:TMP1->pc
-+    |  ins_next1
 +    |  ld KBASE, PC2PROTO(k)(TMP1)
-+    |  ins_next2
++    |  ins_next
 +    |
 +    |6:  // Fill up results with nil.
 +    |  sd TISNIL, 0(TMP2)