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-------------------------------------------------------------------
Tue Nov 11 12:30:12 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.9
* [AMD]
- Adding Ryzen Z2 A and Ryzen AI Z2 Extreme
- [Turin][Dense] Complete the EPYC Embedded 9005 Series
- Adding the Ryzen 5 5500X3D processor
- Complete the Ryzen 8000 Series
- [Zen5][SHP] Introducing the Shimada Peak architecture
- [Family 15h] Provides Package voltage from Core aggregation
* [Intel]
- [Skylake/X] Provides Package voltage from Core aggregation
* [x86_64]
- [Virtualization] Initialized DCU_Mask bitmask
* [aarch64]
- Pass explicit variable-immediate type to fix assembly
* [Build]
- [x86_64] Fedora v34 api fix detecting RHEL MINOR 99
- [Kernel][aarch64] Set mcelsius based on thermal_zone_get_temp()
- [Kernel] Preparing for the impacts of kernel version 6.18
-------------------------------------------------------------------
Wed Aug 6 13:03:56 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- added fix-leap16-compilation.patch to fix compilation on x86_64 Leap 16.0
-------------------------------------------------------------------
Sat Aug 2 13:31:16 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.8
* [Intel]
- [Emerald Rapids] Align MSR entries with Sapphire Rapids
- [Sapphire Rapids] Xeon Scalable 4th gen. startup fix (#560)
* [AMD]
- [Zen5] Introduced a UMC capabilities decoder for STX families
- [Zen5][STX/KRK/STXH] Avoid undefined COF and Power registers
- Switch Zen5/Strix families to the Raphael voltage decoder
- [Zen5/Strix Halo] Probe Memory Controller from DID 0x12b8
- [Zen5][Strix Halo] Adding the RYZEN AI MAX 385
- Add fallback TjMax for legacy CPU families
- Add missing DCU and XPROC_LEAK bitmasks on legacy processors
- [Excavator] Fix setting the scope of temperature to Package
* [aarch64]
- Temperature compilation based on CONFIG_THERMAL
- Getting temperature from the Generic Thermal Management
- Provide the state of WFI/WFE Low Power Methods
- Set the UI comment for PMULL instruction
- Registers requiring a safe access guard (TID3)
- Drop Experimental guard to safely read ID_AA64MMFR3_EL1
- Display detected Interconnect Technology in UI
- Query Cache Coherent Network|Interconnect via DT
- Added multiple Processors and Architectures:
Cortex-A320, Cortex-A520, Cortex-A720AE, Cortex-A725,
Cortex-R82AE, Cortex-X925, Neoverse N3, Neoverse V3,
Neoverse V3AE * ARMv8.1-A, ARMv8.8-A, ARMv9.1-A, ARMv9.2-A,
ARMv9.3-A
- Assign DSU-RTL version according to detected ARM arch.
- Improve detection of Mesh interconnect via DT/ACPI
- Query CMN either from DeviceTree either from ACPI
- JSON export DSU, CMN, CCI, CCN
- Display the presence of the DynamIQ Shared Unit (DSU)
- Added SMT and big.LITTLE labels in the UI footer
* [UI]
- Rephrased string for the CPUID.80000001.ECX[27] feature
- Optimize POWERED() macro with branchless 3-state array lookup
- [aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state
- [CR] In _F4() cast complement mask to the type of bit argument
* [Build]
- [CI] Comment out the unreachable debian-10-buster
- Enforce targets are not built more than necessary
- Clarify Makefile help, info, and version targets
- Support building CoreFreq binaries individually or together
-------------------------------------------------------------------
Thu Jun 5 19:47:58 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.7
* [Kernel]
- Defer the cpufreq get_policy and asm/amd/nb.h changes to v6.16
-------------------------------------------------------------------
Wed Jun 4 19:05:58 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.6
* [Kernel]
- Fix missing cpufreq_get_policy and asm/amd/nb.h in kernel 6.15
- Use VM_DONTEXPAND in mmap() for stability and isolation
* [AMD]
- Decodes voltages of Phoenix families using Rembrandt SVI
- Attempt to read the SoC voltage in Raphael architecture
- Don't probe the HSMP on Raphael' Desktop/Mobile/Embedded
* [Intel]
- Added the Bartlett Lake/S entry
- Clearwater Forest architecture name fix
* [AArch64] [RISC-V] [PowerPC]
- Use exclusive load/store for selected shared variables
* [Doc]
- Obfuscate support email format in README and CLI usage
- Added command line usage instructions to the README
-------------------------------------------------------------------
Sat May 24 11:52:27 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.5
* [Code Review]
- Restrict module parameters to load-time only
* [AMD]
- [Genoa]
- Attempt SOC voltage reading
- Apply monitoring interval to RAM consumption calculation
- [Kernel]
- Use CONFIG_AMD_NB to call SMU if kernel version ≥ 6.0
* [Intel]
- [Core Ultra]
- Updated register names and addresses
- [Alder Lake/N]
- Added "Twin Lake" and "Amston Lake" codenames
* [x86_64]
- Added lock prefix to bit operations for cross-package atomicity
* [AArch64] [RISC-V] [PowerPC]
- Improved CPU topology detection to identify the BSP (Boot Strap Processor)
-------------------------------------------------------------------
Wed May 14 18:27:26 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.3
* [UI]
- Increased length of L3 cache digits in header
- [MC] Renamed Disabled to Undefined channels
- [CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number
- Display N/A when Intel processor is not HDC capable
* [Code Review]
- Refactored variable names for inclusivity
- [Kernel] VT-d: request memory region before use
- uBench: Code clean-up
* [Doc]
- README for Rocky Linux and Clear Linux
* [Build]
- Prevent module loading if detected CPU count > CORE_COUNT (case of EPYC with 384 CPUs)
- Make static the PCI list to comply with kernel frame size
- Kernel 6.15 is switching to use hrtimer_setup()
- [CI] Bump to uraimo version 3
- of_root defined since Kernel 3.19
- Replaced inline C functions with static or macro
- Kernel 6.14 node_to_amd_nb() workaround
- Added CONFIG_ACPI_CPPC_LIB to conditionally build EPP
- Changed some inline function prototypes
* [AMD]
- [Zen]
- Count DIMM ranks from the enabled chip select
- Now conducts Datafabric calls through Kernel PCI
- [HSMP] Provides its own lock rather than SMN' lock
- [HSMP] arguments index fix in CONFIG_AMD_NB build mode
- [HSMP] Check mailbox protocol is correctly functioning using the arithmetic addition 2 + 1 = 3
- Replaced package thermal with a pointer function
- Specifications of some Zen registers
- Adding "Strix Halo" and "Krackan Point" architectures
- Adding "Fire Range" series
- Adding Ryzen Z2 series
- [Genoa]
- Probe up to four memory controllers
- Improved EPYC Genoa support:
- CCD and CCX topology fixed to compute the right thermal SMU address
- Increase BIT_IO_RETRIES_COUNT to parallelize HSMP_RD_DIMM_PWR calls
- Added specifics for an "Eng Sample" of Genoa architecture
- Accumulate the power consumed by RAM
- Attempt to monitor DIMM power consumption from HSMP
- Use generic voltage & power
- [Hawk Point]
- Set AddrCfg & DimmCfg addresses for Phoenix UMC
- [Family 1Ah]
- Added the HSMP for EPYC Turin
* [Intel]
- [MTL][ARL]
- Improving MC Bus and DDR speed to follow OC SOC
- Refactored IMC decoder to query DDR clock
- Merged the P-core and E-core monitoring loops
- Get/Set L1_NPP_Prefetch from MSR_MISC_FEATURE_CONTROL
- Provide monitoring functions to Arrow Lake
Also applying to Lunar Lake
- Grant ODCM and PWR MGMT accesses to MTL, ARL, Lunar Lake
- New features for Core Ultra 7 265K
- [x86_64]
- Order SMBIOS DIMM list by channel
- [IMC] Can display Twelve Channel memory controller
- SMBIOS dump resized to 12 channels multiplied 4 DIMM slots
- Compute the SMBIOS DIMM part number (rev 2)
- Check HCF capability for MPERF/APERF MSR access in VM
* [AArch64] [RISC-V] [PowerPC]
- [riscv64] Fill with the Machine Architecture ID Register marchid
- [ppc64] Added source comment
- [riscv64][ppc64] Improving Hybrid processor detection
- [ppc64] Fix the Carry flag asm code
- [ppc64] The processor version register (PVR) is a 32-bit register
- [ppc64] Use MFXER to get the XER
Raise the Carry Flag
- [ppc64][riscv64] ASM instructions for uBench macros
- [aarch64] Checking CSSELR and CCSIDR registers in ARMv9
- [aarch64] If FEAT_CCIDX implemented read NumSets from upper reg
- [aarch64] Safely access the PMU registers
Detect the Android AVF hypervisor
Comment PMC in uBench macros
- [ppc64] Detect the IBM POWER10 Functional Simulator
- [aarch64][riscv64][ppc64] Improving DT integration to detect VM
- [AArch64] Improving virtualization detection from Device Tree
- [ppc64][riscv64] Device Tree fetching based on kernel version
- [PowerPC] Preliminary port to the ppc64le architecture
- [riscv64] Adding vendor Microchip
- [riscv64] Attempt to read the Hart ID from device tree
- [riscv64] Restore PMU counter delta calculation
- [riscv64] mvendorid & marchid based architecture qualification
- [riscv64] Specification of SSTATUS and SCOUNTEREN registers
- [riscv64] Normalize counters to work with unaccurate QEMU cycles
- [riscv64] Attempt to enable the Cycle and Instruction counters
- [riscv64] Read the performance cycles using rdcycle
- [riscv64] Read the retired instructions counter using rdinstret
- [riscv64] Get the TSC from rdtime instruction
- [riscv64] Comment out any reading of cycles
- [RISC-V] Code clean-up to debug start-up
- [RISC-V] Preliminary port of the riscv64 architecture
-------------------------------------------------------------------
Sun Feb 16 10:27:03 UTC 2025 - Michael Pujos <pujos.michael@gmail.com>
- Update to 2.0.1
* [Build]
- Implement amd_pci_dev_to_node_id from Kernel 6.14
- [CI] Pin build environment to ubuntu-22.04 (thanks @jlacvdr)
- Allow changing WARNING variable from command line (thanks @s-stepien)
* [AMD]
- [Strix Point] Attempt to decode UMC and IOMMU controllers
- [Raphael] Adding Ryzen 5 7400F
- [Granite Ridge] Adding Ryzen 5 9600
-------------------------------------------------------------------
Sun Dec 22 10:32:14 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.8
* [Build]
- [x86_64] AlmaLinux 9.5 (Teal Serval) compilation fix
- [UI] Fix System Registers window for a 3 digits CPU id number
* [Doc]
- SSH how to run the UI
* [AArch64]
- Checking specification of Memory Model Feature Registers
- Aggregate and display ISA features of ID_AA64ISAR3_EL1
- Instruction Set Attribute Register 3 ID_AA64ISAR3_EL1
- Processor Feature Register 2 AA64PFR2_EL1
- Display FP and SIMD bits from MVFR
- Added remaining CLRBHB and PCDPHINT of ISAR2
- Display the Streaming Vector Control Register SVCR
- Query and export the Media and VFP Feature Registers MVFR
- Display, export Floating-point Control Register FPCR
- Architectural Feature Access Control Register CPACR
- Display the Hypervisor Configuration Register HCR_EL2 based on CurrentEL
* [AMD]
- [VERMEER] Adding Ryzen 5 5600XT and 5600T processors
- [Zen 5c] Fixed EPYC Turin-Dense series
-------------------------------------------------------------------
Fri Nov 22 09:42:29 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.7
* [AMD]
- [Family 1Ah][Granite Ridge]
- P-State programming fix
- Merge PCI identifier lists
- Reserve the BTC-NOBR aggregation to Zen2 architecture
* [AArch64]
- Query and JSON export Hypervisor Configuration Register HCR_EL2
- Experimental mode required
-------------------------------------------------------------------
Sat Nov 16 14:22:18 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.6
* [AMD]
- [V2000 Series] Adding the Ryzen Embedded V2A46
- [Family 1Ah][All Families] Refactoring topology for CCD cluster
Confirmed 7950X, 3950X
* [Intel]
- ODCM is confirmed working on Raptor Lake architecture
Confirmed i9-14900K
* [UI]
- Increased max ratio in HWP condition to avoid a zero frequency
Confirmed i9-14900K
* [Build]
- Print other variables from Makefile recipe info
CORE_COUNT
TASK_ORDER
MAX_FREQ_HZ
HWM_CHIPSET
* [CI]
- [AArch64] Commenting out the debian-testing and alpine-latest
* [Doc]
- Mention the AMD family 1Ah support in README
-------------------------------------------------------------------
Fri Nov 8 09:56:48 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.5
* [UI]
- Debugging a target clock ratio selector issue
* [Build]
- Makefile compliant with the -s silent option
- [CI] Disable the unfound arm64v8/ubuntu:rolling
* [AMD]
- [Strix Point] Adding PRO series
- [Zen5][Zen5c] Introducing the TURIN architecture
- Supply a fallback thermal junction max to various Zen series
- [Zen5] Mitigation mechanisms and Features bits
SBPB,
SRSO_NO,
SRSO_USR_KNL_NO,
ERMSB,
FSRS,
FSRC_CMPSB,
PREFETCHI
- [Zen] Added remaining X3D processor models
- [PHOENIX2] Added the unlocked for overclocking Ryzen 5 8500GE
- [PHOENIX2] Added the unlocked for overclocking Ryzen 3 8300GE
- [SIENA] Added the EPYC Embedded 8004 Series
- [GENOA] Added a left over EPYC Embedded 9534
- [Turin] Employed the Genoa UMC decoder
- [Family 1Ah] Updated the PStateDef MSR
- [Zen] Completed CPUID leaf 0x80000021 from PPR 57238
- [Zen5/Granite Ridge] Added Ryzen 7 9800X3D processor
* [Intel]
- [ARL] Declare PCI ids to probe the IMC as a MTL controller
- [ARL][IMC] DDR5: tWR = tWRPRE - tCWL - 10
- [ADL-X/ADL-N] Declare PCI ids to probe the memory controller
- [LNL] Added PCI ids to probe any IMC and SMBUS
- [ARL] Completed with SMBUS PCI id
- [MTL-M] Declare PCI ids to probe the IMC and TCO
- [MTL-M] Set PCI ids into Daemon
- [RPL] Added remaining PX and H processor line platforms
-------------------------------------------------------------------
Fri Sep 20 13:22:21 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.4
* [Build]
- Prevent a collision with macro WRMSRNS within kernel 6.11
* [x86_64]
- [Virtualization] Switch to the HCF or VP_RUNTIME counters depending on the detected hypervisor
-------------------------------------------------------------------
Fri Aug 30 07:47:04 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.3
* [AMD]
- [VMR/RPL/GNR] Voltage Curve Optimizer (VCO)
- Provide a specific VCO formula based on HWM_CHIPSET=AMD_VCO
build parameter
- The standard voltage formulas are restored to these architectures
- Zen5: Guessed a new P-State MSR bits specification to fix the
Coefficient Of Frequency (COF)
-------------------------------------------------------------------
Mon Aug 12 15:07:52 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- Update to 1.98.2
* [Intel]
- [WDT] Adding multiple devices to probe TCO
C620 Series Chipset Production SKUs (0xa1a3)
C620 Series Chipset Super SKUs (0xa223)
Sunrise Point/H (0xa123)
Cannon Lake/LP (0x9da3)
Comet Lake/H (0x06a3)
Ice Lake/LP (0x34a3)
Tiger Lake/H (0x43a3)
Elkhart Lake (0x4b23)
Kaby Lake/H (0xa2a3)
Cannon Lake (0xa323)
Comet Lake/V (0xa3a3)
Ice Lake/NG (0x38a3)
Alder lake/M (0x54a3)
Arrow Lake/S (0x7f23)
Jasper Lake SMBus (0x4da3)
Sunrise Point-LP SMBus (0x9d23)
Comet Lake PCH-LP SMBus (0x02a3)
- MSR_FLEX_RATIO register
Grant access to Alder Lake/H (06_9A)
Deny access to Nehalem/Bloomfield (06_1A)
Removed a condition in access function
-------------------------------------------------------------------
Wed Aug 7 10:07:23 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.98.1
* [AMD]
- [Zen] Inject threshold events when thermal is out of bounds
- Generic Zen architectures renamed with their Family number
- Added a generic entry for the 1A family
- Configure TjMax for multiple Ryzen and Threadripper
- [CR] Optimize AMD temperature filtering function
- [Zen5] Introducing the Eldora architecture aka "Granite Ridge"
- [Zen5] Adding entries for Strix Point
* [Intel]
- Feature-bits of Core Ultra architecture
- [TGL][ADL][RPL] New devices to probe IMC and Watchdog
- [Raptor Lake-E] Adding the IMC probing entries
- Grant full MSR_FLEX_RATIO access to Raptor Lake (06_B7)
- Added Host Bridge DIDs of Raptor Lake-E
- [ADL ... MTL] Code review of IMC decoders
- [ADL] Compute DIMM Bank and Columns on both channels
- [ADL] Process channels differently depending on DDR4 or DDR5
- 12th to 14th generation IMC decoder refactoring
- [ADL ... MTL] Adding Memory Controller Virtual Channel Count
- [ADL ... MTL] Channel count as a function of DDPCD DDR_TYPE
- [ADL ... MTL] Keep all enabled memory controllers
- [12th and superior] Compute tWR quantity as a function of DDR version
* [Build]
- Now leave version number in Makefile
- Pretty print the build and the clean of outputs
Allow the V=n option increase the verbose level (incl. kernel)
- CPU-Freq build against Linux Kernel version 6.11
* [Documentation]
- Refreshed README and Makefile
-------------------------------------------------------------------
Sat Jul 27 11:08:30 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.98.0
* [Build]
- Change dkms configuration to install into /usr/bin/
- Solved compilation with Fedora using RHEL MINOR version number 99
- [CR] Fixed some compilation warnings
- [CR] Fix memory allocation in kernel pages for the SysGate
- Workaround to musl change in basename (#494)
- aarch64: Build with Redhat RHEL version 9
- [CR] x86_64: Prevent array size overflow
- dkms and ckms configuration files upgraded to version 1.98
* [Intel]
- [Raptor Lake] Adding the HB DID of i7-14700K' IMC
- Mitigation mechanism: GDS_NO; RFDS_NO; MONITOR_MITG_NO
- Apply some SDM Documentation Changes
- [MTL] Fix CMD Stretch bit range width
- Added method CLOCK_FLEX_MAX with Xeon's Nehalem & Core 2
- Grants full MSR_FLEX_RATIO access to tested architectures:
- Alder Lake/S
- Tiger Lake/U
- Westmere/Gulftown
- Provides the overclocking bins with unlocked processors
- Query the Overclocking bit (OC) from Capabilities
- Adding technologies: VMD, HDCP, IPU and VPU
- Volume Management Device
- High-Bandwidth Digital Content Protection
- Image Processing Unit
- Vision Processing Unit
- Gaussian & Neural Accelerator - GNA technology
- [CR] Renamed Gemini Lake structures
- [Meteor Lake] Introducing memory controller decoder
* [AArch64]
- Optimizing the Vcore seek
- Workaround to Package discrete voltage: the highest Vcore
- Improving computation of Euclidean division
- Adjust frequency division in CNTFRQ and PMU counters
- Scale a frequency factor from the interval
- Refactoring the frequency ratios for decimal precision
- Compile dev_pm_opp_put if Kernel greater or equal 4.11
- Get the voltage core of CPUs from OPP
* [AMD]
- [Zen4][Raphael] Adding the EPYC 4004 Series
- [Zen4] Clarify Hawk Point and Phoenix-Refresh architectures
- [Family 19h] New voltage formula assigned to model 61h
- Vcore activated
- Voltage SoC deactivated
- [Zen] Prevent the calculation of negative temperature (issue #496)
- [Family 18h] Documented Hygon C86 7375
- [Family 19h] PStateDef specification: Adding VID[8] bit 32
- Specification of MSR HW_PSTATE_STATUS
* [CLI]
- aarch64: Display the state of the Memory Management Unit (MMU)
- aarch64: State of Instruction Cache Unit I$ and Data Cache Unit D$
- Added UI_RULER_MINIMUM & UI_RULER_MAXIMUM building constraints
- Revert "[CLI] Responsive ruler to architectural context"
- This reverts commit 4bc38d6.
- x86_64: AMD Boost and P-States redesigned
- [UI] Hardening missing console/terminal size
- Responsive ruler to architectural context
- x86_64: Make HDCP meaning string shorter
* [Driver]
- Created C2U_Enable as a parameter alias of C1U_Enable
-------------------------------------------------------------------
Fri May 17 15:14:08 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- fix dependency on kernel module that was not versioned
-------------------------------------------------------------------
Thu May 16 09:39:34 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.97.2
* [AMD]
- [Hawk Point] Adding Ryzen PRO processors
- [Phoenix] Adding the unlocked Ryzen 8000 Series
* [Intel]
- [MeteorLake] New bits specified
- EEO and R2H bits inversion fix in MSR_POWER_CTL (0x1fc)
- Reverse specification of MSR UNCORE_PERF_STATUS
- Prefetchers fix of L1 Scrubbing, L1 Next Page and L2 AMP
* [AArch64]
- Providing Exclusive Load/Store to atomic operations
- Improved asm of various macro functions
- Removed LEGACY macros
- Optimized the CORE_COUNT macros
- Marked the Tools feature as nominal: Stress functions available
- Allow user access to Retired Instructions counter
- Fix Instructions counter overflow
- Other PMC enhancements
* [CR]
- Fix a building issue with AlmaLinux aka RHEL-9
- Linux kernel 6.9: Avoid redefinition of Intel MSR macros
* [Doc]
- README section for AlmaLinux
- CONFIG_TRIM_UNUSED_KSYMS kernel build config is forbidden
-------------------------------------------------------------------
Fri Apr 5 20:44:18 UTC 2024 - Michael Pujos <pujos.michael@gmail.com>
- added preamble file for %kernel_module_package macro
- update to 1.97.1
* added aarch64 support
* upstream did not provide a summary changelog. Full list of commits:
https://github.com/cyring/CoreFreq/compare/1.96.5...1.97.1
-------------------------------------------------------------------
Sat Jul 1 08:52:38 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.5
* [AMD]
Adding the "AMD Ryzen 5 5600X3D"
Introducing the Zen4c Bergamo architecture
Specs fixing of Embedded V-series and 3000 Series Processors
Adding MENDOCINO, RAPHAEL Pro, PHOENIX Pro among others
-------------------------------------------------------------------
Thu Jun 15 11:00:33 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.4
* [AMD]
- Display CPUID state of new and legacy features:
Fused Multiply Add [FMA4]
Extended Operation Support [XOP]
Translation Cache Extension [TCE]
Trailing Bit Manipulation [TBM]
OS Visible Work-around [OSVW]
LOCK prefix to read CR8 [AltMov]
* [Intel]
- Advanced Matrix Extensions [AMX]
- Bits and Features of Sierra Forest and Grand Ridge
- Attempt to decode the Meteor Lake Memory Controller
- update to 1.96.3
* [AMD]
- [Zeppelin] Probe more than one UMC controllers on Ryzen Threadripper 1900X
- [Zen4] Dump SMBE and BMEC sub-leaves of CPUID 0x80000020
-------------------------------------------------------------------
Sun Jun 4 08:53:05 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.2
* [Driver]
- Allows compilation to keep going without CONFIG_ACPI_CPPC_LIB
* [Client]
- Adding two command line arguments:
-Op Show Package C-States
-OW Toggle Energy units
* [AMD]
- Specification of some Configuration MSRs
-------------------------------------------------------------------
Sun May 14 16:04:25 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.96.1
* [Driver]
- Postpone Clock Source registration during startup until the Base Clock is computed.
- Change class_create() according to Linux Kernel 6.4
- Clear interrupt flag (cli) after Halt in the Idle method
* [AMD]
- [PHOENIX] Adding Ryzen 7940H, 7840H, 7640H
- [VERMEER] Adding Ryzen PRO and Embedded processors
- Ryzen Z1 CPUID' brand fix
- Adding EPYC Embedded 9004 Series as Genoa
- Adding EPYC Embedded 7003 Series as Milan
- Adding EPYC Embedded 7002 Series as Rome
- Adding EPYC Embedded 7001 Series as Naples
-------------------------------------------------------------------
Wed May 3 15:09:08 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- removed leap_compile_fix.patch no needed anymore
- update to 1.96.0
* [AMD]
[RPL/X3D] Disabling the turbo boosted P-states change
[PHOENIX] Adding Z1, U and HS PRO series.
[Genoa] DAC address at UMC BAR + 0x40
[Zen4] Adding the PCI entries of Genoa
[Zen2] Adding remaining PCI entries
[Zen] Query DAC & CFG with the right UMC base address register
[Zen4] Dump the CPUID Extended CPU Topology leaves.
[Zen][Embedded][Banded Kestrel] R1000 Processor Family
[Zen][Embedded] "Great Horned Owl", "River Hawk", "Grey Hawk"
Complete the "Raven Ridge" and "Picasso" lists
[EPYC] Moved "Snowy Owl" Embedded processors to CPUID 8F_01
[Zen4] introducing Phoenix and Dragon Range
[RMB] adding the Ryzen Embedded V3000 processors
[VMR] adding the "AMD Ryzen 9 PRO 5945"
* [Intel]
Adding Granite Rapids, Sierra Forest, Grand Ridge entries
Adding "Lunar Lake" and "Arrow Lake" entries.
* [UI]
Optimized decimal to digits converter
Allow task tracker to select up to pid_max
Can trace the frozen states of Linux tasks.
Only print HWP frequencies within bounds.
Fix ruler's aggregation.
* [CR]
Check CPUID[HV_PARTITION_PRIVILEGE_MASK] for HV_X64_MSR_VP_RUNTIME
Uninitialized variable fix.
[CPPC] Build EPP with KERNEL_VERSION(6) rather than CONFIG_CACHY
[KERNEL] Linux 6.3: Employ modifier calls with the vma->vm_flags
-------------------------------------------------------------------
Thu Feb 23 18:14:41 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- added leap_compile_fix.patch to fix compilation on Leap
-------------------------------------------------------------------
Wed Feb 22 23:24:52 UTC 2023 - Michael Pujos <pujos.michael@gmail.com>
- update to 1.95.4
* [Intel] [from 11th to 14th gen]
Convert the DRAM Speed to MT/s unit
Compute the Bus Rate based on the BIOS MC PLL
- update to 1.95.3
* [Intel] [Airmont]
Improved the IMC geometry
Introducing the Spreadtrum architecture
Fixed the Bus and DRAM frequency rates
* [Intel] [from 11th to 13th gen] Attempt to probe the interleaved controllers
* [Intel] [Alder Lake/H] Attempt to decode the TCO Watchdog
-------------------------------------------------------------------
Thu Feb 9 16:49:17 UTC 2023 - Dirk Müller <dmueller@suse.com>
- update to 1.95.2:
* Fixed the aggregation of the minimum ratio
Intel:
* [Airmont][Silvermont] Attempt to decode `tCKE` from DRMC
register
* [Airmont] Improve `tWTPr`, `B2B`, `tWWDR` timings
* [Airmont] Provide a new IMC decoder
* Add the Emerald Rapids architecture entry
* [DDR5][DDR4] Add the `RCDw` IMC timing
* [Raptor Lake ] De-activate the MSR Uncore counter
AMD:
* "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenames
* [Zen] Thermal highest limit reset fix
Misc:
* Code review and Registers documentation:
AMD HWCR, Intel HDC and DRP
-------------------------------------------------------------------
Mon Jan 23 08:50:25 UTC 2023 - Dirk Müller <dmueller@suse.com>
- update to 1.95.1:
* [Intel] RPL: voltage of Pcore, Ecore, System Agent
* [Intel] RPL and ADL Chipset device IDs
* [Intel] Decode the RPL IMC and improve DDR5 support
* [Build] Raise `MAX_FREQ_HZ` up to 7125000000 Hertz
* [Intel] Mobile {Coffee Lake, Kaby Lake} codenames
* [Intel] Braswell codename detection
* [AMD] SYSCFG Register
* [AMD] EPYC 9654
* [AMD] Transparent SME
* [AMD] DRAM Data Scrambling
* [AMD] Adding "Barcelo R" and "Rembrandt R"
-------------------------------------------------------------------
Fri Jan 6 10:44:12 UTC 2023 - Dirk Müller <dmueller@suse.com>
- update to 1.94.3:
* [AMD][RMB] If UMC is quad channels then unpopulate odd channels
* [AMD][RPL] Provide Service Processor Vcore as workaround
* [UI] Auto size and lay performance capabilities window
* [UI] Adding comments to the EEO and R2H technologies
* [AMD][Raphael] 7950X3D, 7900X3D. support
-------------------------------------------------------------------
Tue Jan 3 08:19:37 UTC 2023 - Dirk Müller <dmueller@suse.com>
- update to 1.94.1:
* [Intel] Gemini Lake
* [AMD] Ryzen 5 6600 H SoC, UMC channels
* [AMD] Rembrandt: maximum of two UMC channels
* [AMD] Raphael: Decodes DIMM geometry from AddrCfg
* [AMD] Zen: Aggregation refactored
* [AMD] Improved DDR5 clock decoding
* Optimized Idle Loop
-------------------------------------------------------------------
Tue Dec 13 22:58:21 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>
- removed modprobe_corefreqd.service.patch and harden_corefreqd.service.patch
now included in new corefreqd.service file replacing stock one
- update to 1.93.1
* [PRJ] CoreFreq version 1.93.1
* [ACPI/CPPC/EPP] Preview of AMD/Zen Energy Preference (CONFIG_CACHY)
* [UI] Changed the HWP or CPPC ratio bounds.
* [FIX] Putting `corefreqd` in the root cgroup (issue #379) Thanks to gel-crabs
* [DOC] Parameters to blacklist the amd_pstate since kernel 6.0.11
* [AMD][Zen4] Apply a voltage formula based on Rembrandt's. (#378)
* [AMD][Zen4/Raphael] Attempting temperature per CCD from TCTL+0x308
* [AMD][Zen4] Changed Timer loop
* [CR] CLI code review and UI optimizations
* [UI] Auto refresh the Topology items when off/online
* [CR] Conditionally build with additional PMC Counters
* [Intel] Adding Z8000 System Memory Controller Registers
* [CR] Transformed global variable in cells padding
* [UI] Windows re-scaling fix
* [UI] Apply color theming to the CPPC capabilities list.
* [AMD][Raphael] Adding device DIDs to probe UMC and IOMMU
* [CPPC/FMW] Computes value bounds while Enabling/Disabling firmware
* [CR] CPPC lib errors are now raised to Debug level
* [AMD][Zen4] Increased the UMC size to 12 channels.
* [CPPC] Handles the OffLine CPU case.
* [CLI] Refactoring HWP/CPPC to print all capabilities per CPU
* [ACPI] Computes the CPPC Bounds
* [Intel] Linear Address Masking (LAM)
* [CLI] EFER: Left aligned labels
* [AMD] Reports UAIE and AIBRSE bits from EFER system register
* [CLI] Changed mitigation mechanisms incapability labels
* [AMD][Zen2] Mitigation Mechanism BTC-NOBR * ACPI/OSPM documentation
* [CR] Code review on bit masks
* [CPPC][ACPI] Kernel may decode the Guaranteed Performance Register
* [UI] Optimize the cycles to clear the time bar.
* [CR] Code review for extra compiler warnings
* [UI] Time of the day displayed in the right side of menu
* [UI] Display the current date and time in menu bar
* [Kernel] Introducing support of `CONFIG_SCHED_BORE`
* [CLI] Fixing ambiguous CPPC report: hardware vs firmware
* [CLI] Surrounds _CPC feature with square brackets
* [CPPC] Provides the ACPI _CPC object state.
* [UI] Colors the task being tracked in the tracking list
* [UI] Display the current time in the menu bar
* [CLI] Reserve the programmable TDP section to Intel processors.
* [AMD/Zen3+] Improving the DIMM geometry of Rembrandt UMC
-------------------------------------------------------------------
Mon Dec 5 08:53:55 UTC 2022 - Dirk Müller <dmueller@suse.com>
- update to 1.92.4:
* [Intel/Skylake-X] Permits MSR_RING_PERF_LIMIT_REASONS
-------------------------------------------------------------------
Fri Nov 4 14:32:03 UTC 2022 - Jan Engelhardt <jengelh@inai.de>
- Repair deficient description grammar.
-------------------------------------------------------------------
Fri Nov 4 13:35:40 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>
- update to version 1.92.3
- Export CPUID bits Intel Sierra Forest, Grand Ridge, Granite Rapids
and completes AMD64 Fn0000_0007_ECX_x0
- [Features] WBNOINVD and CLZERO instructions
- Adding various Mitigation Mechanism aggregations:
IPRED_DIS_U, IPRED_DIS_S, RRSBA_DIS_U, RRSBA_DIS_S, BHI_DIS_S, MCDT_NO
- RDPID and UMIP capability fixed.
- [AMD] Perf. Mon. version based on CPUID_0x80000022.EAX.PerfMonV2
- [AMD][Zen3+][Rembrandt] Trigger UMC and IOMMU decoders
- [AMD][Ryzen 5 6600H] Found voltage VID @ SMU 0x6f010 and 0x6f014
- Introducing AMD Security Feature capabilities:
SKINIT, SEV, GMET, SEV-ES, SEV-SNP
- [AMD64] Non-architectural MSR: SPECULATIVE STORE BYPASS DISABLE
- [Intel][2nd & 3rd gen] Misc IMC optimizations
- [AMD][Rembrandt] Provides Vcore from a new formula.
- Dumping CPUID leaves from AMD64 Architecture Programmer’s Manual
- [Intel][HSW & BDW] Compute the DIMM banks
- [UI] Re-assigned keys to move or resize windows.
- [AMD][Zen] Uncore frequency: Improving the Memory Clock divisor
- [Intel][HSW & BDW][SKL] Make use of same function DimmWidthToRows
- [AMD][Zen3+][Rembrandt] Provides the thermal sensor.
- [AMD/Zen2 & Zen3] Removed the HSMP capability.
- [Intel][CML][RKL][TGL] Compute the DIMM Rows from CH_WIDTH
- [AMD/EPYC] Adding the CPUID of Zen4 Genoa architecture
- [AMD/Zen2] Introducing Mendocino architecture
- Changed MeteorLake/N to CPUID 06_B5
- [Intel] Computes BIOS DRAM frequency based on PLL_REF100
- [Intel][SNB/IVB/HSW/BDW] Improved BIOS DRAM frequency
- [Intel][SNB/IVB] DRAM frequency based on RAM_Select and FSB_Select
- [Intel][IVB] IMC specifications and optimizations.
- [Intel][SNB,IVB] Computes the DIMM A from DAS bit in MAD register
- [Intel][SNB,IVB,HSW,BDW] Rolling back changes to the DIMM topology
- [Intel][BDW][HSW] Query the IMC Power Down Mode
- [Intel][IVB][SNB] Attempt to decode the IMC third timings
- [AMD][Ryzen] Added AMD Ryzen 7 PRO 6860Z
- [AMD][F17h-F19h] Can toggle ON and OFF the Instruction Cache Unit
- [AMD] Checking the Ryzen "OEM Only" processors
- [Intel] Specification of 12th Gen. MSR registers capability
- [Intel] Adding Raptor Lake-S with CPUID 06_BF
- [AMD] Introducing Zen 4 / Raphael architecture
- [Intel][SNB,IVB,HSW] Attempt to assign the Rank per DIMM slot
- [Intel][SNB,IVB,HSW] Attempt to fix the DIMM(s) topology layout
- ClockSource: TSC udelay() asm implementation builtin as a default
- [Intel][Alder Lake] Adding IMC entry for i5-12500 processor
- [Intel][Alder Lake] Added default case if Processor has only Pcores
- [Intel][Atom/Bonnell][IMC] Attempt to compute the DIMM geometry
- [UI][Custom view] Show the Uncore unit in watt or joule
- [UI] Display HWP or CPPC in footer for capable processors.
- [CLI] Added HWP Capabilities and HWP Request to the JSON export
- [CLI] Don't allow the HWP dialog box if feature is not available.
- [CPPC][Firmware] allows (de)activation of the feature.
- [CLI] Added CPU ratios to JSON export
- [CPPC] Improved scaling
- [CPPC] Build fixed down to Kernel version 3
- [Kernel/ACPI] Attempt to write CPPC registers
-------------------------------------------------------------------
Mon Aug 22 15:48:08 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.91.6
- [AMD/Zen][UMC] Fixed the Mem Clock and ECC regressions
- Designate the Package identifier in Power consumed readings
- [Intel/ADL/IMC] Guessing activated channel from the populated DIMM
- [AMD][UMC, IOMMU] Adding missing DID of family 19h devices
- [AMD_DataFabric_Cezanne] Removed the Experimental mode
- Intel/ADL/IMC: Fixing the Memory Channels count
- [AMD/Zen] Improved UMC mapping. Threadripper 3960X issue
- Avoid some NULL pointer strings during SMBIOS decoding
-------------------------------------------------------------------
Wed Jun 22 19:35:21 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.91.3
* No changelog was made available by upstream
-------------------------------------------------------------------
Mon Mar 7 11:57:34 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>
- removed non-working leap15_2.patch and leap15_3.patch:
Leap 15.4 is the minimum supported version
- Update to version 1.90.1
* support for Alder Lake architecture:
in particular, specialized monitoring for Pcore and Ecore
* more precise DDR5 and DDR4 timings from SKL to ADL:
introduction of "Gear mode"
* improvement using Power Limiters:
zero W on PL1 & PL2; DRAM clampig marked experimental
* characteristics for Zen architecture:
CPPC; C1E; MEM CLOCK in raw frequency
* C-state Core for Ice Lake/X
* various characteristics of C-state package for AMD/Zen and Intel (Lake)
* various changes in UI
* non-regression tests for kernels 5.16.12 and 5.17.rc6
-------------------------------------------------------------------
Sat Feb 12 22:26:56 UTC 2022 - Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.89.3
* No changelog was made available by upstream
-------------------------------------------------------------------
Sun Oct 10 14:37:04 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.87.4
- fixed service hardening preventing daemon to start (boo#1191509)
- added modprobe_corefreqd.service.patch to load/unload kernel
module on service start/stop. Do not load module on boot anymore
- fixed leap15_3.patch including unnessary junk
-------------------------------------------------------------------
Tue Sep 7 10:17:46 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>
- Update to version 1.87.1
-------------------------------------------------------------------
Tue Jul 27 09:50:10 UTC 2021 - Johannes Segitz <jsegitz@suse.com>
- Added hardening to systemd service(s). Added harden_corefreqd.service.patch
-------------------------------------------------------------------
Sat Jul 3 13:22:03 UTC 2021 - Ferdinand Thiessen <rpm@fthiessen.de>
- Update to version 1.86.7
* AMD/Zen: Improve SMT counters built on VPMC
* AMD/Matisse & Zen3: Can alter the Power Limit with a PL1 offset
* AMD/SMU: Provides the firmware and interface version
* AMD HSMP: Support Host System Management Port.
* AMD IOMMU Base Address Register fix.
* Intel/Nehalem: Altering the TDC limit
* Intel: Integration of the 11th Generation
* UI: Stream buffer memory overlap fix.
* UI: Support color theming and introducing the Strawberry theme.
* Driver: New 'CPU_Count' argument
* New parameter "WDT_Enable" to toggle the Watchdog Timer.
* Page fault fix when unregistering idle device percpu structure
* Avoid a kernel zero division in clocksource_register_khz()
* Various bug fixes and minor improvements
-------------------------------------------------------------------
Sat May 8 12:00:09 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>
- updated to v1.84.5
Fixes compilation on kernel 5.12
See commits on https://github.com/cyring/CoreFreq/commits/master
for full change list
-------------------------------------------------------------------
Thu Apr 15 09:55:08 UTC 2021 - Michael Pujos <pujos.michael@gmail.com>
- updated to v1.84.1
See commits on https://github.com/cyring/CoreFreq/commits/master
for changes list
- added patch leap15_3.patch: fix failure to build on Leap 15.3
-------------------------------------------------------------------
Thu Dec 31 14:56:39 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- updated to git 20201229.
See commits on https://github.com/cyring/CoreFreq/commits/master
for changes list
-------------------------------------------------------------------
Wed Oct 28 12:43:05 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- updated to git 20201028, fixes compilation on kernel 5.9
-------------------------------------------------------------------
Mon Sep 14 19:33:07 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- updated changelog to mention leap15_2.patch
-------------------------------------------------------------------
Mon Sep 14 11:25:44 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- updated to git 20200914, fixes compilation on kernel 5.8
-------------------------------------------------------------------
Tue Aug 18 15:31:19 UTC 2020 - Dominique Leuenberger <dimstar@opensuse.org>
- Fix invalid usage of %{_libexecdir} for systemd owned paths below
%{_prefix}/lib.
-------------------------------------------------------------------
Tue Jul 14 13:41:15 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- added patch leap15_2.patch: fix failure to build on Leap 15.2
- fix failure to build on Tumbleweed
- updated to 1.79.9 + current git
-------------------------------------------------------------------
Fri Apr 17 22:50:23 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- updated to 1.75.2 current git to fix compilation on kernel 5.6.x
-------------------------------------------------------------------
Thu Mar 5 10:38:04 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- updated to 1.73.7
- do not use git version anymore
- added %systemd_requires
- remove unneeded unzip BuildRequires
-------------------------------------------------------------------
Wed Feb 19 22:53:29 UTC 2020 - Michael Pujos <pujos.michael@gmail.com>
- Initial version from git 20200219
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