From 34c3675d67fb99d6dc720cc221be20c1c1252c2e4928015941b8def2669a179d Mon Sep 17 00:00:00 2001 From: Stefan Dirsch Date: Wed, 18 Sep 2013 07:39:51 +0000 Subject: [PATCH] Accepting request 199428 from home:sumski:branches:X11:XOrg Added U_radeon-pad-CS-to-8-DW.patch from upstream -- aligns the IB to 8 DWs. r6xx also require at least 4 DW alignment to avoid a hw bug. OBS-URL: https://build.opensuse.org/request/show/199428 OBS-URL: https://build.opensuse.org/package/show/X11:XOrg/Mesa?expand=0&rev=327 --- Mesa.changes | 9 +++ Mesa.spec | 3 + ...insys-pad-IBs-to-a-multiple-of-8-DWs.patch | 68 +++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch diff --git a/Mesa.changes b/Mesa.changes index ed4965d..b94c0f9 100644 --- a/Mesa.changes +++ b/Mesa.changes @@ -1,3 +1,12 @@ +------------------------------------------------------------------- +Tue Sep 17 17:50:56 UTC 2013 - hrvoje.senjan@gmail.com + +- Added U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch from + upstream -- aligns the gfx, compute, and dma IBs to 8 DW boundries. + Additionally, r6xx hardware requires at least 4 + DW alignment to avoid a hw bug. This also aligns the DMA + IBs to 8 DW which is required for the DMA engine. + ------------------------------------------------------------------- Mon Sep 16 12:44:53 UTC 2013 - sndirsch@suse.com diff --git a/Mesa.spec b/Mesa.spec index 8e88131..3b4c147 100644 --- a/Mesa.spec +++ b/Mesa.spec @@ -111,6 +111,8 @@ Patch15: u_mesa-8.0-llvmpipe-shmget.patch # PATCH-FIX-UPSTREAM gallium-egl-gbm-use-wayland-cflags.patch -- use pkgconfig for finding wayland Patch16: u_gallium-egl-gbm-use-wayland-cflags.patch Patch18: U_wayland-egl-pc-require-wayland.patch +# PATCH-FIX-UPSTREAM U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch -- from http://cgit.freedesktop.org/mesa/mesa/commit/?id=a81beee37e0dd7b75422448420e8e8b0b4b76c1e +Patch19: U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch BuildRoot: %{_tmppath}/%{name}-%{version}-build @@ -534,6 +536,7 @@ rm -rf docs/README.{VMS,WIN32,OS2} %patch16 -p1 %endif %patch18 -p1 +%patch19 -p1 %build diff --git a/U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch b/U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch new file mode 100644 index 0000000..296b59a --- /dev/null +++ b/U_radeon-winsys-pad-IBs-to-a-multiple-of-8-DWs.patch @@ -0,0 +1,68 @@ +From a81beee37e0dd7b75422448420e8e8b0b4b76c1e Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 6 Sep 2013 16:43:34 -0400 +Subject: [PATCH 1/1] radeon/winsys: pad IBs to a multiple of 8 DWs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This aligns the gfx, compute, and dma IBs to 8 DW boundries. +This aligns the the IB to the fetch size of the CP for optimal +performance. Additionally, r6xx hardware requires at least 4 +DW alignment to avoid a hw bug. This also aligns the DMA +IBs to 8 DW which is required for the DMA engine. This +alignment is already handled in the gallium driver, but that +patch can be removed now that it's done in the winsys. + +Reviewed-by: Marek Olšák +Signed-off-by: Alex Deucher +CC: "9.2" +CC: "9.1" +--- + src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 30 +++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +index ea0c99d..38a9209 100644 +--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c ++++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +@@ -466,6 +466,36 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags, ui + struct radeon_drm_cs *cs = radeon_drm_cs(rcs); + struct radeon_cs_context *tmp; + ++ switch (cs->base.ring_type) { ++ case RING_DMA: ++ /* pad DMA ring to 8 DWs */ ++ if (cs->ws->info.chip_class <= SI) { ++ while (rcs->cdw & 7) ++ OUT_CS(&cs->base, 0xf0000000); /* NOP packet */ ++ } else { ++ while (rcs->cdw & 7) ++ OUT_CS(&cs->base, 0x00000000); /* NOP packet */ ++ } ++ break; ++ case RING_GFX: ++ /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements ++ * r6xx, requires at least 4 dw alignment to avoid a hw bug. ++ */ ++ if (flags & RADEON_FLUSH_COMPUTE) { ++ if (cs->ws->info.chip_class <= SI) { ++ while (rcs->cdw & 7) ++ OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */ ++ } else { ++ while (rcs->cdw & 7) ++ OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */ ++ } ++ } else { ++ while (rcs->cdw & 7) ++ OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */ ++ } ++ break; ++ } ++ + if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) { + fprintf(stderr, "radeon: command stream overflowed\n"); + } +-- +1.8.4 +