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- U_r300g-Set-R300_VAP_CNTL-on-RSxxx-to-avoid-triangle-flickering.patch:

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Initialize RSxxx chipsets correctly (bsc#985650)

OBS-URL: https://build.opensuse.org/package/show/X11:XOrg/Mesa?expand=0&rev=541
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Max Staudt 2016-10-14 10:19:13 +00:00 committed by Git OBS Bridge
parent 12a58d062e
commit 6cd013da6f
3 changed files with 76 additions and 0 deletions
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6
Mesa.changes
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@ -1,3 +1,9 @@
-------------------------------------------------------------------
Fri Oct 14 10:17:17 UTC 2016 - mstaudt@suse.com
- U_r300g-Set-R300_VAP_CNTL-on-RSxxx-to-avoid-triangle-flickering.patch:
Initialize RSxxx chipsets correctly (bsc#985650)
-------------------------------------------------------------------
Fri Oct 14 09:10:46 UTC 2016 - mstaudt@suse.com

3
Mesa.spec
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@ -71,6 +71,8 @@ Patch15: u_mesa-8.0-llvmpipe-shmget.patch
Patch18: n_VDPAU-XVMC-libs-Replace-hardlinks-with-copies.patch
# never to be upstreamed
Patch21: n_Define-GLAPIVAR-separate-from-GLAPI.patch
# Already upstream
Patch22: U_r300g-Set-R300_VAP_CNTL-on-RSxxx-to-avoid-triangle-flickering.patch
# Nouveau multithreading workarounds from https://github.com/imirkin/mesa/commits/locking
Patch61: N_01-WIP-nouveau-add-locking.patch
Patch62: N_02-nouveau-more-locking-make-sure-that-fence-work-is-always-done-with-the-push-mutex-acquired.patch
@ -589,6 +591,7 @@ rm -rf docs/README.{VMS,WIN32,OS2}
%patch12 -p1
%patch18 -p1
%patch21 -p1
%patch22 -p1
%patch61 -p1
%patch62 -p1
%patch63 -p1

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U_r300g-Set-R300_VAP_CNTL-on-RSxxx-to-avoid-triangle-flickering.patch Normal file
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From: Max Staudt <mstaudt@suse.de>
Date: Thu Sep 8 01:53:45 2016 +0200
Subject: [PATCH]r300g: Set R300_VAP_CNTL on RSxxx to avoid triangle flickering
Patch-mainline: 02675622b02742960678c438f1b239321c075f50
Git-repo: git://anongit.freedesktop.org/mesa/mesa
References: bsc#985650
Signed-off-by: Max Staudt <mstaudt@suse.de>
On the RSxxx chip series, HW TCL is missing and r300_emit_vs_state()
is never called.
However, if R300_VAP_CNTL is never set, the hardware (at least the
RS690 I tested this on) comes up with rendering artifacts, and
parts that are uploaded before this "fix" remain broken in VRAM.
This causes artifacts as in fdo#69076 ("triangle flickering").
It seems like this setup needs to happen at least once after power on
for 3D rendering to work properly. In the DDX with EXA, this happens in
RADEON_SWITCH_TO_3D() when processing an XRENDER Composite or an
Xv request. So playing back a video or starting a GTK+2 application
fixes 3D rendering for the rest of the session. However, this auto-fix
doesn't happen when EXA is not used, such as with GLAMOR or Wayland.
This patch ensures the register is configured even in absence of
the DDX's EXA module.
The register setting is taken from:
xf86-video-ati -- RADEONInit3DEngineInternal()
mesa/src/mesa/drivers/dri/r300 -- r300EmitClearState()
Tested on RS690.
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Max Staudt <mstaudt@suse.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
src/gallium/drivers/r300/r300_context.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 82ba043..0998fac 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -190,7 +190,7 @@ static boolean r300_setup_atoms(struct r300_context* r300)
/* VAP. */
R300_INIT_ATOM(viewport_state, 9);
R300_INIT_ATOM(pvs_flush, 2);
- R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
+ R300_INIT_ATOM(vap_invariant_state, is_r500 || !has_tcl ? 11 : 9);
R300_INIT_ATOM(vertex_stream_state, 0);
R300_INIT_ATOM(vs_state, 0);
R300_INIT_ATOM(vs_constants, 0);
@@ -314,6 +314,14 @@ static void r300_init_states(struct pipe_context *pipe)
if (r300->screen->caps.is_r500) {
OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
+ } else if (!r300->screen->caps.has_tcl) {
+ /* RSxxx:
+ * Static VAP setup since r300_emit_vs_state() is never called.
+ */
+ OUT_CB_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
+ R300_PVS_NUM_CNTLRS(5) |
+ R300_PVS_NUM_FPUS(2) |
+ R300_PVS_VF_MAX_VTX_NUM(5));
}
END_CB;
}