Accepting request 1079377 from home:eeich:branches:utilities
- Update to release 20230406:
* Fixed bug when interpreting leaf 0xb and 0x1f bit widths:
Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1
in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
values.
* For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
level & previous levels" to reflect this definition.
* Support APIC bit fields for the newest 4 topology
layers: module, tile, die, die group. And for the mp version, also
the older cu & pkg levels.
* Use the extended APIC ID's when available in a variety of leaves.
* Support leaf 0xb method for AMD/Hygon.
* Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
* Added 7/1/edx AMX-COMPLEX instructions.
* Added 7/2/edx UC-lock disable.
* Added 0x10/n/ecx non-contiguous 1s value supported.
* Added 0x1c/ecx event logging supported bitmap.
* Added 0x23/0/ebx decoding.
* Decode 0x80000026/1/ebx core type & native model.
* For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
Intel versions in 7/1/eax.
* For 0x80000022/ecx, shorten description, show bitmask only in
hex.
* Update CPUID utility with new feature bits as documented in
the AMD Processor Programming Reference for Family 19h and Model 11h:
0x8000000a/edx extended LVT offset fault change
0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
FsGsKernelGsBaseNonSerializing
0x80000022/ebx number of available UMC PMCs
0x80000022/ecx bitmask representing active UMCs
OBS-URL: https://build.opensuse.org/request/show/1079377
OBS-URL: https://build.opensuse.org/package/show/utilities/cpuid?expand=0&rev=45
This commit is contained in:
Git OBS Bridge
parent
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version https://git-lfs.github.com/spec/v1
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oid sha256:b89b41f8895d0d58fdbb0a54102bb490bc7c5828db2cd15be82d14d19463a579
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size 141652
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3
cpuid-20230406.src.tar.gz
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cpuid-20230406.src.tar.gz
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version https://git-lfs.github.com/spec/v1
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oid sha256:f4045de535f30e34e8c012b054ce66f40ac399144d6e3c3896bd80c0deeef1b0
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size 147932
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120
cpuid.changes
120
cpuid.changes
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-------------------------------------------------------------------
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Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <eich@suse.com>
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- Update to release 20230406:
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* Fixed bug when interpreting leaf 0xb and 0x1f bit widths:
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Interpret as bit *offsets*, not *widths* of leaf 4. This fixes off by 1
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in (APIC width synth) and incorrectly shifted (APIC synth) PKG_ID & CORE_ID
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values.
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* For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
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level & previous levels" to reflect this definition.
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* Support APIC bit fields for the newest 4 topology
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layers: module, tile, die, die group. And for the mp version, also
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the older cu & pkg levels.
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* Use the extended APIC ID's when available in a variety of leaves.
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* Support leaf 0xb method for AMD/Hygon.
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* Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
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* Added 7/1/edx AMX-COMPLEX instructions.
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* Added 7/2/edx UC-lock disable.
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* Added 0x10/n/ecx non-contiguous 1s value supported.
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* Added 0x1c/ecx event logging supported bitmap.
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* Added 0x23/0/ebx decoding.
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* Decode 0x80000026/1/ebx core type & native model.
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* For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
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Intel versions in 7/1/eax.
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* For 0x80000022/ecx, shorten description, show bitmask only in
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hex.
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* Update CPUID utility with new feature bits as documented in
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the AMD Processor Programming Reference for Family 19h and Model 11h:
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0x8000000a/edx extended LVT offset fault change
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0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
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FsGsKernelGsBaseNonSerializing
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0x80000022/ebx number of available UMC PMCs
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0x80000022/ecx bitmask representing active UMCs
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* Differentiate preliminary (uarch synth) for (0,6),(10,10);
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(0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores
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from their Redwood Cove counterparts.
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* Added preliminary (synth) & (uarch synth) for (0,6),(12,6)
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Lion Cove & Skymont, from LX*.
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* Added 12/0/eax SGX ENCLS EUPDATESVN bit.
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* Added 0x1f/*/ecx level type value "die group (6)".
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* Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D &
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E0 steppings from coreboot*.
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* Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen
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Xeons to Ice Lake-SP. Also, improved decoding for engr samples where
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the brand string omits Xeon & Bronze/Silver/Gold/Platinum.
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* Improved (synth) decoding for (0,6),(11,14) Intel N-Series.
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* Differentiate (synth) & (uarch synth) for (0,6),(11,14)
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Alder Lake-N based on core type, much like for other Alder Lake models.
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This corrects the cores to Gracemont. As for Golden Cove, perhaps
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P-cores never will exist for this model but, if they do, they should
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now be decoded correctly.
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* Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P.
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* Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P.
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* Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made
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the following (synth) changes:
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* Updated (0,6),(3,7),8 Bay Trail with stepping name C0.
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* Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping.
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* Corrected (0,6),(4,6),1 Crystal Well to C0 stepping.
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* Updated (0,6),(4,7),1 Broadwell to include E0 stepping.
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* Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable).
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* Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable).
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* Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable).
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* Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0
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steppings.
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* Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable).
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* Added (0,6),(6,12),1 Ice Lake B0.
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* Updated (0,6),(8,6),4 Snow Ridge with stepping B0.
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* Updated (0,6),(8,6),5 Snow Ridge with stepping B1.
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* Added (0,6),(8,6),1 Lakefield B2/B3 stepping.
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* Corrected (0,6),(8,12),1 Tiger Lake stepping to B1.
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* Added (0,6),(8,12),2 Tiger Lake C0.
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* Added (0,6),(8,14),10 Coffee Lake D0.
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* Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping.
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* Added (0,6),(8,15) Sapphire Rapids numerous steppings.
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* Updated (0,6),(9,12) Jasper Lake with stepping A1.
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* Differentiate (0,6),(8,10) Lakefield P-cores from Tremont
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E-cores, much as I previously did for Alder Lake & Raptor Lake.
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* For known Hybrid chips (Alder Lake, Raptor Lake & Lakefield),
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only decode the uarch if it's one of the two known hybrid types.
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However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only),
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so also decode core type == 0x00 there.
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* In the Intel Core era, uarch families are identified only by
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the initial uarch in the family. So the family names in {braces},
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which also are uarch names, can be confusing. So, change (synth) and
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(uarch synth) for those families to explain the relationships between
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the subsequent uarch and the initial uarch, in the form of
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"shrink of", "optim of", and the unusual "backport of".
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* Added (4th Gen) to the (synth) description of (10,15),(1,*)
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AMD EPYC Genoa.
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* Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2
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CPUs to claim 4nm process.
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* Corrected 7/1/eax fast REP instructions, where I'd left the
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REP prefix out of the description.
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* Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and
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Event Deliver (FRED).
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* Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf
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0x23 is valid.
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* Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based
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on sample from bakerlab.org, which I missed on Oct 3 2022, when I
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added the (synth) decoding.
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* Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family
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19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and
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(7,0) Phoenix, based on their respective PPPR's.
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* Added very early (synth) decoding for Lunar Lake. There is
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no corresponding (uarch synth) decoding, because no name is yet known
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for the uarch.
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* Added (0,6),(9,10) Alder Lake Core names: i*-12000.
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* Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont
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E-cores from Golden Cove P-cores.
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* Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15)
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Raptor Lake Gracemont E-cores from Raptor Cove P-cores.
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* Added (synth) & (uarch synth) decoding for (10,15),(7,8)
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Phoenix 2, from Coreboot*.
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* Decode Xen tsc mode.
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* Added (synth) decoding for (10,15),(6,1,1) Raphael B1.
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-------------------------------------------------------------------
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Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller <dmueller@suse.com>
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- updaet to 20230120:
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- updated to 20230120:
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* Intel's 13th Generation Core datasheet provides stepping names as
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well as numbers! So:
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* cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
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@ -101,7 +217,7 @@ Sat Aug 13 10:39:31 UTC 2022 - Jan Engelhardt <jengelh@inai.de>
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- Update to release 20220812
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* Corrected (synth) decoding for (0,6),(8,6) Intel Snow
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Ridge/Parker Ridge.
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Ridge/Parker Ridge.
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* Added 8000000a/edx X2AVIC flag
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* Generalized (0,6),(8,14),9,YP stepping case to include
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Pentium 4425Y, from instlatx64 sample.
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@ -17,7 +17,7 @@
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Name: cpuid
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Version: 20230120
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Version: 20230406
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Release: 0
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Summary: x86 CPU identification tool
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License: GPL-2.0-or-later
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