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-------------------------------------------------------------------
Mon Aug 5 16:05:55 UTC 2024 - Valentin Lefebvre <valentin.lefebvre@suse.com>
- Update to release 20240716
* cpuid.c: For AMD Zen CPUs, overhauled uarch & synth decoding to
determine the CPU model from only the extended model & high bit of the
model field. Also, determine the stepping (revision) mechanically
from the low-order 3 bits of the model and the stepping number.
This should correctly identify retail Zen 5 Ryzen's. This also
corrects some stepping bugs from the Zen 1 era.
- Update to release 20240709
* cpuid.c: Added 6/eax IA32_HWP_CTL MSR supported.
* cpuid.c: Added 7/2/edx MONITOR perf unaffected by tbl overflow.
* cpuid.c: Added synth decoding for Hygon Dhyana B1 & C2. Still no
information on a uarch name for these, so decode_uarch_hygon() remains
silent for them.
* cpuid.c: Added uarch synth decoding for (0,6),(5,5),11 Cooper Lake.
The synth decoding was already present. Its absence from
decode_uarch_intel was just an oversight.
* cpuid.c: Fixed division-by-zero error in decode_mp_synth Intel leaf
1/4 (zero fallback). This is meant for old, incomplete cpuid -r
dumps, but even for hand-crafted dumps, determining 0 cores and then
dividing by that 0 is unacceptable.
- Update to release 20240409
* cpuid.c: Added 0x8000000a/edx PMC virtualization.
* cpuid.c: Added 0x8000000a/edx idle HLT intercept.
* cpuid.c: Added 0x8000001f/eax PMC virtual support for SEV-ES/SNP.
* cpuid.c: Added 0x8000001f/eax mention of SEV-SNP to existing fields.
* cpuid.c: Added 0x8000001f/eax RMPREAD instruction.
* cpuid.c: Added 0x8000001f/eax secure AVIC support.
* cpuid.c: Added 0x8000001f/eax allowed SEV features support.
* cpuid.c: Added 0x8000001f/eax write to hypervisor in-used allowed.
* cpuid.c: Added 0x8000001f/eax IBPB on entry support.
* cpuid.c: Added Siena to (10,15),(10,x) synth decoding, based on 58268
Arch Overview.
* cpuid.man: Added 58268: AMD EPYC 8004 Series Architecture Overview.
* cpuid.c: Added preliminary (10,15),(7,12) Hawk Point synth decoding.
* cpuid.c: Fixed spelling: EPGR->EGPR (extended GPR's).
- Update to release 20240330
* cpuid.c: Added 5/ecx monitorless MWAIT.
* cpuid.c: Added 7/1/edx user-timer events.
* cpuid.c: Added 7/1/edx AVX10 instructions.
* cpuid.c: Added 7/1/edx APX advanced performance extensions.
* cpuid.c: Added 7/1/edx MWAIT instruction (overrides 1/ecx[3]).
* cpuid.c: Added Intel-specific print_instr_synth_intel to determine
presence of MWAIT from 1/ecx and/or 7/1/edx.
* cpuid.c: Updated 12/n/ecx section property values 1 & 3.
* cpuid.c: Added 14/0/ebx PTTT processor trace trigger tracing.
* cpuid.c: Added 14/1/eax number of IA32_RTIT_TRIGGERx_CFG MSRs,
including D4_IMAGES decoding.
* cpuid.c: Added 14/1/ecx flags.
* cpuid.c: Added MINUS24_IMAGES decoding for 0xf/1/eax QoS monitoring
counter size.
* cpuid.c: Added 0x23/1 sub-header: Architecture Performance Monitoring
Extended Counters Supported Bitmaps (0x23/1), and simplified fields.
* cpuid.c: Added 0x23/2 sub-header: Architecture Performance Monitoring
Extended Auto Counter Reload (ACR) Bitmaps (0x23/2), expanded on
existing field descriptions, and added "can cause reloads" fields.
* cpuid.c: Added 0x24 leaf: Converged Vector ISA.
* cpuid.c: Added to print_d_n: new XSAVE area: 19 for APX EPGR
(extended general purpose registers).
* cpuid.man: Added new Intel 355828 (APX) doc.
* cpuid.c: Added uarch decoding for (11,15),(1,0), which is mentioned
with (11,15),(0,0) in the title of 58088 AMD 1Ah Models 00h-0Fh and
Models 10h-1Fh ACPI v6.5 Porting Guide.
* cpuid.c: Expanded br.xeon test to include brands with "XEON", and
br.scalable to include "BRONZE", "PLATINUM", etc. (all caps), based on
Emerald Rapids (engr?) sample. I don't know if this is a change Intel
will use moving forward, or a quirk of engr samples, but checking for
it is harmless enough.
- Update to release 20240324
* cpuid.c: Updated synth decoding for (0,6),(12,15),2 Emerald Rapids
A1/R1.
* cpuid.man: Added new Intel docs.
* cpuid.c: In do_real(), for the 0x1b leaf, add a sanity check to avoid
infinite recursion if a hypervisor never reports invalid (0) on any
subleaf. The sanity check checks for a subleaf identical to its
predecessor, which is not reasonable.
* cpuid.c: Added synth & uarch decoding for (0,6),(13,13) Clearwater
Forest.
* cpuid.c: Updated (0,6),(8,12),1 to include stepping B0, from ILPMDF*
* cpuid.c: Updated (0,6),(11,15),5 to Raptor Lake stepping H0, based on
preponderance of evidence.
* cpuid.c: Added synth decoding for (0,6),(10,10) Core Ultra CPUs.
* cpuid.c: Updated (0,6),(11,7) to include Core i*-14000. Some CPUs
having this branding, and it's not clear what's different from the
Core i*-13000 versions. The steppings don't seem to matter.
Inspection suggests maybe CET_SSS.
* cpuid.c: Corrected synth decoding for (10,15),(1,8) Storm Peak: Ryzen
Threadripper 7000.
* cpuid.c: Added synth decoding for (10,15),(7,5),2 AMD Ryzen Phoenix F2.
* cpuid.c: Added very preliminary uarch decoding for (10,15),(6,0) and
(10,15),(7,0), both Zen 5.
* cpuid.c: Changed preliminary synth decoding for (0,6),(11,5) to Arrow
Lake, based on Intel SDE 9.33.0.
* cpuid.c: Added synth decoding for (0,6),(8,13),0 Tiger Lake-H P0
stepping.
* cpuid.c: Added synth decoding for (0,6),(11,13),0 Lunar Lake A0
stepping.
* cpuid.c: Changed uarch decoding for (0,6),(13,13) to Darkmont, the
presumed uarch for Clearwater Forest.
* cpuid.c: Added 12/1/eax AEX attribute enabled, as described by Scott
Raynor, Intel.
* cpuid.c: Added 7/1/eax NMI-source reporting.
* cpuid.c: Added 7/1/eax INVD prevention after BIOS done.
* cpuid.c: Renamed 7/1/ebx PKNDKB instruction.
* cpuid.c: Added 7/1/edx URDMSR, UWRMSR instructions.
* cpuid.c: Added 0xa/ebx additional events.
* cpuid.c: Added 0xf/1/eax non-CPU agent features.
* cpuid.c: For 0xf/0/edx supports L3 cache monitoring, removed
redundant "QoS".
* cpuid.c: Renamed print_10_n_{eax,ecx} -> print_10_12_{eax,ecx}.
* cpuid.c: Added 0x10/0/ebx cache bandwidth allocation supported.
* cpuid.c: Replaced 0x10/{1,2}/ecx: non-CPU agent support.
* cpuid.c: Renamed 0x10/{1,2}/ecx: non-contiguous bitmask supported.
* cpuid.c: Added 0x10/5 Cache Bandwidth Allocation decoding.
* cpuid.c: Renamed 0x23/0/ebx IA32_PERFEVTSELx EQ bit supported.
* cpuid.c: Added 0x23/2 ACR counters bitmaps.
* cpuid.c: Corrected synth decoding for (10,15),(10,x) to EPYC (4th Gen)
(server CPUs), instead of Ryzen (desktop CPUs).
* cpuid.c: Added (0,6),(12,12) Panther Lake synth decoding from LX*, but
left out corresponding uarch decoding which is alls rumors currently:
maybe Panther Cove, Cougar Cove, or something else.
* cpuid.c: Added hypervisor+0xc ebx isolation type new value: TDX (3)
from LX*.
* cpuid.c: Added (11,5),(0,0) Zen 5 uarch from LX*.
* cpuid.c: To decode_uarch_intel, added (0,6),(11,12) & (0,6),(11,13)
Lion Cove & Skymont as uarch underpinning Lunar Lake.
* cpuid.c: Added 0x80000021/eax selective branch prediction barrier,
PRED_CMD[IBPB] flushes branch type preds. They appear to be only
synthetic flags provided for hypervisor guests!
* cpuid.c: Added 0x80000021/eax CPU not affected by SRSO flag, from LX*.
* cpuid.c: Added (10,15),(8&9,0) uarch & synth decoding for AMD Instinct
MI300, from LKML: https://lkml.org/lkml/2023/7/20/668 patches.
In the past, Instinct MI* described just the GPU, but they seem to be
conflating them into a product name here.
* cpuid.: Added prelim uarch decoding for (11,15),(2,0) & (11,15),(4,0),
both Zen 5, based on engr samples. No synth decoding yet, because it
isn't known yet.
* cpuid.c: Added prelim synth decoding for (0,6),(11,12) Lunar Lake from
Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def. No uarch decoding, because
Lunar Lake uarch name is not known yet.
* cpuid.c: Added prelim synth decoding for (0,6),(9,5) Sapphire Rapids
from Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def.
* cpuid.c: Added synth decoding for (0,6),(11,7),0 Raptor Lake A0
stepping, from Coreboot*.
* cpuid.c: Added 7/1/eax SHA512, SM3 & SM4 instructions.
* cpuid.c: Added 7/1/ebx TSE PBNDKB instruction.
* cpuid.c: Added 7/1/ebx AVX-VNNI-INT16 instructions.
* cpuid.c: Added 7/1/edx UIRET flexibly updates UIF.
* cpuid.c: Added 0x1b/2 TSE target.
* cpuid.c: Corrected sub-leaf walk of leaf 0x1b to stop immediately if
sub-leaf 0 is invalid.
* cpuid.c: Added (uarch synth) & (synth) decoding for (0,6),(12,5)
Arrow Lake based on Lion Cove & Skymont.
* cpuid.c: Added 0x80000008/ebx IBPB_RET.
* cpuid.c: Renamed 0x8000000a/edx extended LVT AVIC access changes.
* cpuid.c: Renamed 0x8000000a/edx guest VMCB addr check.
* cpuid.c: Added 0x8000000a/edx bus lock threshold.
* cpuid.c: Renamed several 0x80000020 leaves & fields.
* cpuid.c: Added 0x80000020/0/ebx assignable bandwidth monitoring
counters.
* cpuid.c: Added 0x80000020/0/ebx SDCI allocation enforcement
* cpuid.c: Added 0x80000020/5 PQoS Assignable Bandwidth Monitoring
Counters.
* cpuid.c: Added (synth) decoding for (0,6),(10,10),4 Meteor Lake-M C0
stepping from Coreboot*
-------------------------------------------------------------------
Wed Jun 21 09:18:20 UTC 2023 - Valentin Lefebvre <valentin.lefebvre@suse.com>
- Update to release 20230614
* Improved (synth) identification for Intel Xeon Scalable (3rd
Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
Arizona Beach.
* Made the (simple synth) fields non-default. The (simple synth)
fields still are available, but only with the -S/--simple
option.
- Update to release 20230505
* Fixed CPU counts for higher levels
not dividing out counts from lower levels.
* Differentiate Core i3-N300 N-Series from ordinary N-Series.
* Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
space I/O, based on LX*.
* Added (synth) decoding for Xeon W version of Sapphire Rapids,
Meteor Lake-M B0.
* Added (synth) & (uarch synth) Emerald Rapids family: Raptor
Cove, and Granite Rapids family: Redwood Cove.
-------------------------------------------------------------------
Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <eich@suse.com>
- Update to release 20230406:
* Support APIC bit fields for the newest 4 topology layers:
module, tile, die, die group.
* Support leaf 0xb method for AMD/Hygon.
* Added prelim Bergamo A1 stepping from sample.
* Added AMX-COMPLEX instructions, UC-lock disable,
non-contiguous 1s value support, event logging supported
bitmap.
* Update CPUID utility with new feature bits as documented in
the AMD Processor Programming Reference for Family 19h and
Model 11h: extended LVT offset fault cange, enhanced
predictive store forwarding, FSRS, FSRC,
FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
bitmask representing active UMCs.
* Added (synth) decoding for Sapphire Rapids D & E0 steppings
* Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
Raptor Lake-H/U/P.
* Differentiate (synth) & (uarch synth) for (0,6),(11,14)
Alder Lake-N based on core type.
* Differentiate Lakefield P-cores from Tremont E-cores.
* Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
* Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
* Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
Cezanne/Barcelo, Raphael, and Phoenix, based on their
respective PPPRs.
* Added Alder Lake Core names: i*-12000.
* Decode Xen tsc mode.
-------------------------------------------------------------------
Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller <dmueller@suse.com>
- updated to 20230120:
* Intel's 13th Generation Core datasheet provides stepping names as
well as numbers! So:
* cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
* cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
steppings, and clarified case for unknown stepping.
* cpuid.man: Added 743844: 13th Generation Core datasheet.
* cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
* cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
* cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
* cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
* cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
* cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
* cpuid.c: Added several 7/2/edx bits.
* cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
* cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
relevant for XCR0.
* cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
hex bitmask.
* cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
* cpuid.c: Renamed 0x1a: Native Model ID.
* cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake
from MSR_CPUID_table*.
* cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
based on instlatx64 sample.
* cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
Emerald Rapids CPUs.
* cpuid.c: Added 7/1/eax LASS: linear address space separation.
* cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
should use minus-one notation.
* cpuid.c: Certain leaves cannot be displayed correctly in isolation,
i.e. without information about other leaves saved in the stash. For
example, the display for leaf 3 uses bits saved from leaf 1. If the
-l/--leaf option is used to restrict cpuid to reading only a single
leaf, such leaves now are displayed as raw hex, rather than with
incorrect information. This is handled by passing a NULL stash to
print_reg() and below, and by many new checks for a NULL stash.
* cpuid.c: Updated cache associativity strings used in 0x80000006 and
0x80000019 leaves to use value ranges, as in AMD docs.
* cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
0x80000020/0 register EBX, not ECX.
* cpuid.c: Added 0x80000026/0/edx extended APIC ID.
* cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from
AMD 57095 revision guide.
* cpuid.man: Added AMD 57095 revision guides, and some older guides that
I'd forgotten.
-------------------------------------------------------------------
Mon Dec 05 09:50:12 UTC 2022 - Valentin Lefebvre <valentin.lefebvre@suse.com>
- Update to release 20221201
* Clarified synth decoding for Intel Xeon D-1700.
* Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
instlatx64 sample.
* Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
* Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
* Added synth & uarch decoding for (10,15),(10,1) Bergamo.
* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
* Added 0x8000001f/eax bits: RMPQUERY instruction support,
VMPL supervisor shadow stack support, VMGEXIT parameter support,
virtual TOM MSR support, IBS virtual support for SEV-ES guests,
SMT protection support, SVSM communication page MSR support,
VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
* Added 0x80000020/0/ecx bit: L3 range reservation support.
* Added 0x80000021/eax bits: automatic IBRS,
CPUID disable for non-privileged.
* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
* Added 0x80000022/ebx field: number of LBR stack entries.
* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
* Added 0x80000026 leaf: AMD Extended CPU Topology.
* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
AMD LBR V2 flag, from LX*.
-------------------------------------------------------------------
Thu Oct 13 14:05:28 UTC 2022 - Valentin Lefebvre <valentin.lefebvre@suse.com>
- Update to release 20221003
* Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
* Added synth & uarch synth decoding for
* (0,6),(11,5) Intel Meteor Lake
* (0,6),(11,6) Intel Grand Ridge (Crestmont)
* (0,6),(11,14) Intel Granite Rapids
* Renamed 7/0/eax enh hardware feedback to just "Thread
Director".
* Added 7/1/eax instructions.
* Added 0x12/0/eax SGX ENCLU EDECCSA flag.
* Added 0x23 Architecture Performance Monitoring Extended leaf
decoding.
* Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
* Added synth decoding for (10,15),(6,1) Raphael
* Fixed title for AMD 0x8000001a leaf: Performance Optimization
identifiers.
-------------------------------------------------------------------
Sat Aug 13 10:39:31 UTC 2022 - Jan Engelhardt <jengelh@inai.de>
- Update to release 20220812
* Corrected (synth) decoding for (0,6),(8,6) Intel Snow
Ridge/Parker Ridge.
* Added 8000000a/edx X2AVIC flag
* Generalized (0,6),(8,14),9,YP stepping case to include
Pentium 4425Y, from instlatx64 sample.
* Added support for hypervisor+3/ecx (Microsoft) flags.
-------------------------------------------------------------------
Thu Feb 24 21:10:05 UTC 2022 - Andreas Stieger <andreas.stieger@gmx.de>
- update to 20220224:
* Support for AMD Rembrandt E1
* Add hypervisor+4/eax (Xen) expanded destination id bit
* Correction for Alder Lake, Rocket Lake decoding
* Multiple detection and decodings updated
-------------------------------------------------------------------
Mon Nov 15 22:04:30 UTC 2021 - Andreas Stieger <andreas.stieger@gmx.de>
- update to 20211114:
* Many updated and added identified CPU models and variants
* Updated hypervisor support
-------------------------------------------------------------------
Thu Oct 8 08:19:24 UTC 2020 - Josef Möllers <josef.moellers@suse.com>
- Update to 20201006:
Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
"Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
as well as some additional decoding of supported features.
[cpuid-20201006.src.tar.gz, jsc#sle-13189]
-------------------------------------------------------------------
Tue Apr 28 18:54:25 UTC 2020 - Andreas Stieger <andreas.stieger@gmx.de>
- update to 20200427:
* Add synth decoding for AMD Steppe Eagle/Crowned Eagle
(Puma 2014 G-Series), based on instlatx64 sample
* Add 7/0/edx SERIALIZE & TSXLDTRK bit descriptions
* Add 0xf/1/eax Counter width & overflow flag
* Add 0x10/3/ecx per-thread MBA controls flag
* Add 0x8000001f fields
* Add AMD 24594 & 40332 docs
* Correct field lengths in 14/0 and 14/1 subleafs so that
columns line up
* Add CC150 (Coffee Lake R0) synth decoding, based on
instlatx64 example
* Add Jasper Lake A0 stepping (from Coreboot*)
* Update 1/ebx "cpu count" to modern terminology: "maximum
addressible IDs for CPUs in pkg" to avoid user confusion
* Update 4/eax CPU & core count terminology in the same way
-------------------------------------------------------------------
Fri Mar 6 08:24:45 UTC 2020 - Jan Engelhardt <jengelh@inai.de>
- Update to release 20200211
* Zhaoxin decoding
* Name enhancements for models from AMD, VIA, Intel, NSC
* Added SEV cpuid bit.
-------------------------------------------------------------------
Fri Jan 17 13:06:18 UTC 2020 - Josef Möllers <josef.moellers@suse.com>
- Upgrade to release 20200116
many changes in Changelog: many new flags added.
Also added support for Cyrix MediaGX, Matisse B0 stepping,
Hygon CPUs.
[cpuid-20200116.src.tar.gz]
-------------------------------------------------------------------
Sat May 19 23:47:56 UTC 2018 - jengelh@inai.de
- Update to new upstream release 20180519
* Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields.
* Added 7/ecx bit 16: 5-level paging.
* Improved 14/0/ecx descriptions.
* Added hypervisor leaf descriptions from Microsoft's
Hypervisor Top Level Functional Specification (Released
Version 5.0b).
* Added CPUID features documented in PPR for AMD Family 17h
Model 01h B1 (54945 Rev 1.14):
* Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated
instruction).
* Added bits to 80000001/ecx (amd).
* Added bits to 80000007/edx, 8000000a/edx, 8000001a/eax,
8000001b/eax.
* Added 80000007/ebx, 80000007/ecx, 80000008/ebx.
* Added tentative 8000001f descriptions.
-------------------------------------------------------------------
Fri Apr 20 06:33:28 UTC 2018 - josef.moellers@suse.com
- Update to new upstream release 20180419
* Added synth decoding for AMD Zen, Pentium Silver (Gemini
Lake), Xeon Scalable (Bronze, Silver, Gold, Platinium)
(Skylake), Core X-Series (Skylake-X), Bay Trail D0, Bay Trail
A0, Xeon E7-4800/8800 (Broadwell-EX B0), Xeon D-1500N
(Broadwell-DE A1), Bay Trail-I (E3800), Avoton C0 stepping.
* Corrected synth decoding for Bay Trail-M C0 steppings.
* Added new Intel 1b leaf from Intel Architecture.
* Added various bit fields.
-------------------------------------------------------------------
Mon Jan 23 09:54:56 UTC 2017 - jengelh@inai.de
- Update to new upstream release 20170122
* Added synth decoding for Intel Knights Landing B0.
* Added new synth decodings for Intel Kaby Lake.
* Fixed synth decodings for AMD Steamroller and Jaguar.
* Added synth decodings for AMD Puma and Excavator.
* For (6,15),(0,2) Piledriver processors, detect FX series and
report it as Vishera instead of Abu Dhabi/Seoul/Delhi.
* Added general microarchitecure names for AMD (e.g.
Piledriver) in addition to specific core names (e.g. Trinity)
for later generation processors. If I have trouble
remembering these, it seems likely other people do too.
* Added synth decoding for Quark X1000.
* Added Intel Atom Z2760 (Clover Trail).
* Added extra synth decodings for some Ivy Bridge and Sandy
Bridge processors.
-------------------------------------------------------------------
Fri Dec 2 08:55:37 UTC 2016 - jengelh@inai.de
- Update to new upstream release 20161201
* Fixed bugs in the subleaf walks for 0x8000001d (AMD cache
information) and 0x40000003 (Xen hypervisor information) because
the code for them was under wholly the wrong loops.
-------------------------------------------------------------------
Tue Nov 15 08:43:11 UTC 2016 - jengelh@inai.de
- Update to new upstream release 20161114
* cpuid.c: Added -l/--leaf and -s/--subleaf options to cause
cpuid to dump just the specified leaf and subleaf. If
-s/--subleaf is not specified, it is assumed to be 0. The
intended purpose for this is to display raw dumps of
not-yet-supported leaves.
* cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and
CLWB decoding to 7/ebx.
* cpuid.c: Added AVX512VBMI to 7/ecx.
* cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring
support.
* cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx.
* cpuid.c: Added 0x15/ecx nominal core crystal clock decoding.
* cpuid.c: In print_17_0_ebx, corrected reversed scheme
encodings.
* cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0
stepping.
* cpuid.c: Added synth decoding comment about Braswell D1
stepping, but its stepping number is not documented.
* cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake
processors.
* cpuid.c: Added synth decoding for Apollo Lake processors.
* cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake
processors.
* cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags.
* cpuid.c: Add Knights Mill (KNM) CPUID.
-------------------------------------------------------------------
Tue Aug 30 08:57:28 UTC 2016 - jengelh@inai.de
- Update to new upstream release 20160814
* cpuinfo2cpuid: Added a script that takes input from a
/proc/cpuinfo file and converts it into suitable input to
cpuid. The information that cpuid is capable of producing based
on this very limited input information is slight, but
apparently there is interest in getting the synthesized (synth)
leaf from this.
* Support SGX, MPX, BNDLDX/BNDSTX, RDPID, and IA32_XSS PT state.
* Add information for Skylake, Broadwell, Broadwell-E and -EX
processors, Atom C2000 (Avoton) with A0/A1 steppings, Atom
Z3n00 (Bay Trail) stepping 1, Xeon D-1500 (Broadwell-DE) V2
stepping, corrected Atom Z8000 (Cherry Trail), added Atom S1200
(Centerton) and VIA Eden.
-------------------------------------------------------------------
Sat Nov 7 11:37:43 UTC 2015 - jengelh@inai.de
- Update to new upstream release 20151017
* Updated synth decoding for Broadwell processors.
* Added 0xd leaf field.
* Updated and expanded 0x14 leaf fields.
* Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX).
* Added synth decoding for Intel Core i5/i7 (Skylake).
* Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d.
* added synth decoding for Knights Landing.
* Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx.
* Renamed 0xf leaves to include "Monitoring".
* Added 0x10 leaves for QoS Enforcement.
* Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3.
* Added missing i7 synth decoding for (0,6),(3,14).
* Corrected Atom Z3000 model & stepping which were bafflingly
wrong: (0,6)(3,5),1 -> (0,6)(3,7),8.
* Corrected other Bay Trail stepping names for Celeron/Pentium
N and J series.
* Added synth decoding for Intel Xeon Phi (Knights Corner).
* Added synth decoding for Intel Atom C2000 (Avoton).
* Added synth decoding for Intel Xeon E5-x600 (Haswell-EP).
* Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP).
* Added synth decoding for Intel Core M (Broadwell-Y).
* Added synth decoding for Intel Xeon D-1500 (Broadwell-DE).
* Added synth decoding for Intel i7-5000 Extreme (Haswell R2).
* Added synth decoding for Intel Atom Z8000 (Cherry Trail).
* Added synth decoding for Intel Pentium/Celeron N3000
-------------------------------------------------------------------
Tue Jun 9 16:25:47 UTC 2015 - jengelh@inai.de
- Update to new upstream release 20150606
* Support for several leaf updates, including information on
XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. Decoding for
more Haswell processors, Broadwell, Cherry Trail, and Avoton.
- %doc is already implicit for manpages
-------------------------------------------------------------------
Mon Aug 12 10:33:26 UTC 2013 - jengelh@inai.de
- Update to new upstream release 20130610
* Add lost Opteron 3200 strings
-------------------------------------------------------------------
Mon Jun 10 14:01:53 UTC 2013 - jengelh@inai.de
- Update to new upstream release 20130609
* support for many new CPU types
- Wrap description at 70 cols; remove redundant %clean section
-------------------------------------------------------------------
Wed Jun 1 22:05:31 UTC 2011 - pascal.bleser@opensuse.org
- update to 20110305
- moved to utilities
-------------------------------------------------------------------
Sat Dec 22 00:00:00 UTC 2007 - guru@unixtech.be
- moved to openSUSE Build Service
-------------------------------------------------------------------
Mon Sep 18 00:00:00 UTC 2006 - guru@unixtech.be
- new upstream version
-------------------------------------------------------------------
Wed Aug 23 00:00:00 UTC 2006 - guru@unixtech.be
- new upstream version
-------------------------------------------------------------------
Tue Aug 8 00:00:00 UTC 2006 - guru@unixtech.be
- new upstream version
-------------------------------------------------------------------
Mon Jul 31 00:00:00 UTC 2006 - guru@unixtech.be
- added binary stripping on SUSE < 9.3
- removed Packager and Distribution, injected by rpmmacros
- new upstream version
-------------------------------------------------------------------
Mon Apr 3 00:00:00 UTC 2006 - guru@unixtech.be
- new package

57
cpuid.spec Normal file
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#
# spec file for package cpuid
#
# Copyright (c) 2024 SUSE LLC
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
# upon. The license for this file, and modifications and additions to the
# file, is the same license as for the pristine package itself (unless the
# license for the pristine package is not an Open Source License, in which
# case the license is the MIT License). An "Open Source License" is a
# license that conforms to the Open Source Definition (Version 1.9)
# published by the Open Source Initiative.
# Please submit bugfixes or comments via https://bugs.opensuse.org/
#
Name: cpuid
Version: 20240716
Release: 0
Summary: x86 CPU identification tool
License: GPL-2.0-or-later
Group: System/Management
URL: http://etallen.com/cpuid.html
Source: http://etallen.com/cpuid/%name-%version.src.tar.gz
BuildRequires: gcc
BuildRequires: glibc-devel
BuildRequires: make
ExclusiveArch: %ix86 x86_64
%description
cpuid executes the CPUID instruction on x86-family CPUs and decodes
the results into English descriptions. It knows about Intel, AMD, and
Cyrix CPUs, and is fairly complete.
%prep
%autosetup
%build
# remove -Werror=format-security which is used on Mandriva, as it produces
# a false positive compiler error on several printf calls:
CFLAGS=$(echo "%optflags -Wall" | sed 's/-Werror=format-security//g')
%make_build CFLAGS="$CFLAGS"
%install
mkdir -p "%buildroot/%_bindir" "%buildroot/%_mandir/man1"
install -pm0755 cpuid cpuinfo2cpuid "%buildroot/%_bindir/"
install -pm0644 cpuid.man "%buildroot/%_mandir/man1/cpuid.1"
%files
%doc ChangeLog
%license LICENSE
%_bindir/*
%_mandir/man1/*.1*
%changelog