14 lines
590 B
Diff
14 lines
590 B
Diff
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diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
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index 39fce7b..1821774 100644
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--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
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+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
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@@ -55,7 +55,7 @@
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* Guarantees that the LOAD and STORE operations generated before the
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* barrier occur before the LOAD and STORE operations generated after.
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*/
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-#define rte_mb() {asm volatile("sync" : : : "memory"); }
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+#define rte_mb() asm volatile("sync" : : : "memory")
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/**
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* Write memory barrier.
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