diff --git a/fwts-V19.06.00.tar.gz b/fwts-V19.06.00.tar.gz
deleted file mode 100644
index b8600a6..0000000
--- a/fwts-V19.06.00.tar.gz
+++ /dev/null
@@ -1,3 +0,0 @@
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-oid sha256:13aa991f12c69f48df368aae5e5d0fbc9136413b4bfe115421bc3216d919f8a2
-size 3784598
diff --git a/fwts-V19.07.00.tar.gz b/fwts-V19.07.00.tar.gz
new file mode 100644
index 0000000..4c39967
--- /dev/null
+++ b/fwts-V19.07.00.tar.gz
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:9b7f3cde180fa811a27564b7628e4074d339d4c45ba34b7e838fa6da23362bee
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diff --git a/fwts.changes b/fwts.changes
index 4208489..0b4cd23 100644
--- a/fwts.changes
+++ b/fwts.changes
@@ -1,3 +1,20 @@
+-------------------------------------------------------------------
+Tue Aug 13 08:07:06 UTC 2019 - Martin Pluskal <mpluskal@suse.com>
+
+-  Update to version 19.07.00:
+  * cpu/msr: add 3 more CPU IDs for IA32_silvermont_MSRs
+  * cpu/msr: check SGX & LMCE in IA32_FEATURE_CONTROL (3ah)
+  * cpu/msr: move TSC_ADJUST (3bh) to IA32_MSRs
+  * cpu/msr: add SMM_MONITOR_CTL (9bh) to IA32_MSRs
+  * cpu/msr: add MC*_CTL2 MSR registers
+  * cpu/msr: add VMX_VMFUNC MSR register
+  * cpu/msr: add MISC_ENABLE MSR to IA32_atom_MSRs
+  * cpu/msr: add MSR_PMG_IO_CAPTURE_BASE to IA32_silvermont_MSRs
+  * cpu/msr: add MSR_FEATURE_CONFIG to IA32_silvermont_MSRs
+  * cpu/msr: add MSR_TEMPERATURE_TARGET to IA32_silvermont_MSRs
+  * cpu/msr: add MSR_BBL_CR_CTL3 to IA32_silvermont_MSRs
+  * ACPICA: Update to version 20190703
+
 -------------------------------------------------------------------
 Tue Jul 23 10:15:09 UTC 2019 - Martin Pluskal <mpluskal@suse.com>
 
diff --git a/fwts.spec b/fwts.spec
index 40feddc..eead4aa 100644
--- a/fwts.spec
+++ b/fwts.spec
@@ -17,7 +17,7 @@
 
 
 Name:           fwts
-Version:        19.06.00
+Version:        19.07.00
 Release:        0
 Summary:        Firmware Test Suite
 License:        GPL-2.0-or-later