- Update to version 19.07.00:
* cpu/msr: add 3 more CPU IDs for IA32_silvermont_MSRs * cpu/msr: check SGX & LMCE in IA32_FEATURE_CONTROL (3ah) * cpu/msr: move TSC_ADJUST (3bh) to IA32_MSRs * cpu/msr: add SMM_MONITOR_CTL (9bh) to IA32_MSRs * cpu/msr: add MC*_CTL2 MSR registers * cpu/msr: add VMX_VMFUNC MSR register * cpu/msr: add MISC_ENABLE MSR to IA32_atom_MSRs * cpu/msr: add MSR_PMG_IO_CAPTURE_BASE to IA32_silvermont_MSRs * cpu/msr: add MSR_FEATURE_CONFIG to IA32_silvermont_MSRs * cpu/msr: add MSR_TEMPERATURE_TARGET to IA32_silvermont_MSRs * cpu/msr: add MSR_BBL_CR_CTL3 to IA32_silvermont_MSRs * ACPICA: Update to version 20190703 OBS-URL: https://build.opensuse.org/package/show/hardware/fwts?expand=0&rev=93
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-------------------------------------------------------------------
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Tue Aug 13 08:07:06 UTC 2019 - Martin Pluskal <mpluskal@suse.com>
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- Update to version 19.07.00:
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* cpu/msr: add 3 more CPU IDs for IA32_silvermont_MSRs
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* cpu/msr: check SGX & LMCE in IA32_FEATURE_CONTROL (3ah)
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* cpu/msr: move TSC_ADJUST (3bh) to IA32_MSRs
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* cpu/msr: add SMM_MONITOR_CTL (9bh) to IA32_MSRs
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* cpu/msr: add MC*_CTL2 MSR registers
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* cpu/msr: add VMX_VMFUNC MSR register
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* cpu/msr: add MISC_ENABLE MSR to IA32_atom_MSRs
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* cpu/msr: add MSR_PMG_IO_CAPTURE_BASE to IA32_silvermont_MSRs
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* cpu/msr: add MSR_FEATURE_CONFIG to IA32_silvermont_MSRs
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* cpu/msr: add MSR_TEMPERATURE_TARGET to IA32_silvermont_MSRs
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* cpu/msr: add MSR_BBL_CR_CTL3 to IA32_silvermont_MSRs
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* ACPICA: Update to version 20190703
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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Tue Jul 23 10:15:09 UTC 2019 - Martin Pluskal <mpluskal@suse.com>
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Tue Jul 23 10:15:09 UTC 2019 - Martin Pluskal <mpluskal@suse.com>
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