diff --git a/cross-aarch64-gcc7.changes b/cross-aarch64-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-aarch64-gcc7.changes
+++ b/cross-aarch64-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-aarch64-gcc7.spec b/cross-aarch64-gcc7.spec
index 65065d1..e45de0b 100644
--- a/cross-aarch64-gcc7.spec
+++ b/cross-aarch64-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-arm-gcc7.changes b/cross-arm-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-arm-gcc7.changes
+++ b/cross-arm-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-arm-gcc7.spec b/cross-arm-gcc7.spec
index d9aeba0..3b3fb13 100644
--- a/cross-arm-gcc7.spec
+++ b/cross-arm-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-arm-none-gcc7-bootstrap.changes b/cross-arm-none-gcc7-bootstrap.changes
index 101bba7..4da2297 100644
--- a/cross-arm-none-gcc7-bootstrap.changes
+++ b/cross-arm-none-gcc7-bootstrap.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-arm-none-gcc7-bootstrap.spec b/cross-arm-none-gcc7-bootstrap.spec
index eb7d71f..6bb781b 100644
--- a/cross-arm-none-gcc7-bootstrap.spec
+++ b/cross-arm-none-gcc7-bootstrap.spec
@@ -484,6 +484,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-arm-none-gcc7.changes b/cross-arm-none-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-arm-none-gcc7.changes
+++ b/cross-arm-none-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-arm-none-gcc7.spec b/cross-arm-none-gcc7.spec
index a1a46f7..65fa3b2 100644
--- a/cross-arm-none-gcc7.spec
+++ b/cross-arm-none-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-avr-gcc7-bootstrap.changes b/cross-avr-gcc7-bootstrap.changes
index 101bba7..4da2297 100644
--- a/cross-avr-gcc7-bootstrap.changes
+++ b/cross-avr-gcc7-bootstrap.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-avr-gcc7-bootstrap.spec b/cross-avr-gcc7-bootstrap.spec
index 2d83b49..c1fddcc 100644
--- a/cross-avr-gcc7-bootstrap.spec
+++ b/cross-avr-gcc7-bootstrap.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-avr-gcc7.changes b/cross-avr-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-avr-gcc7.changes
+++ b/cross-avr-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-avr-gcc7.spec b/cross-avr-gcc7.spec
index 243b5c1..f65f441 100644
--- a/cross-avr-gcc7.spec
+++ b/cross-avr-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-epiphany-gcc7-bootstrap.changes b/cross-epiphany-gcc7-bootstrap.changes
index 101bba7..4da2297 100644
--- a/cross-epiphany-gcc7-bootstrap.changes
+++ b/cross-epiphany-gcc7-bootstrap.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-epiphany-gcc7-bootstrap.spec b/cross-epiphany-gcc7-bootstrap.spec
index a5b8a81..8089a99 100644
--- a/cross-epiphany-gcc7-bootstrap.spec
+++ b/cross-epiphany-gcc7-bootstrap.spec
@@ -484,6 +484,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-epiphany-gcc7.changes b/cross-epiphany-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-epiphany-gcc7.changes
+++ b/cross-epiphany-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-epiphany-gcc7.spec b/cross-epiphany-gcc7.spec
index faca860..86c2962 100644
--- a/cross-epiphany-gcc7.spec
+++ b/cross-epiphany-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-hppa-gcc7.changes b/cross-hppa-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-hppa-gcc7.changes
+++ b/cross-hppa-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-hppa-gcc7.spec b/cross-hppa-gcc7.spec
index 9e9330b..7caba74 100644
--- a/cross-hppa-gcc7.spec
+++ b/cross-hppa-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-i386-gcc7.changes b/cross-i386-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-i386-gcc7.changes
+++ b/cross-i386-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-i386-gcc7.spec b/cross-i386-gcc7.spec
index f2cc378..e3eb923 100644
--- a/cross-i386-gcc7.spec
+++ b/cross-i386-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-m68k-gcc7.changes b/cross-m68k-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-m68k-gcc7.changes
+++ b/cross-m68k-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-m68k-gcc7.spec b/cross-m68k-gcc7.spec
index 7436393..04b4bbf 100644
--- a/cross-m68k-gcc7.spec
+++ b/cross-m68k-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-mips-gcc7.changes b/cross-mips-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-mips-gcc7.changes
+++ b/cross-mips-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-mips-gcc7.spec b/cross-mips-gcc7.spec
index ffe77ee..748c65b 100644
--- a/cross-mips-gcc7.spec
+++ b/cross-mips-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-nvptx-gcc7.changes b/cross-nvptx-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-nvptx-gcc7.changes
+++ b/cross-nvptx-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-nvptx-gcc7.spec b/cross-nvptx-gcc7.spec
index ea7f3d0..7e69c9f 100644
--- a/cross-nvptx-gcc7.spec
+++ b/cross-nvptx-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-ppc64-gcc7.changes b/cross-ppc64-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-ppc64-gcc7.changes
+++ b/cross-ppc64-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-ppc64-gcc7.spec b/cross-ppc64-gcc7.spec
index 20c89cb..6e9a67e 100644
--- a/cross-ppc64-gcc7.spec
+++ b/cross-ppc64-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-ppc64le-gcc7.changes b/cross-ppc64le-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-ppc64le-gcc7.changes
+++ b/cross-ppc64le-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-ppc64le-gcc7.spec b/cross-ppc64le-gcc7.spec
index 22cb6b1..0db1525 100644
--- a/cross-ppc64le-gcc7.spec
+++ b/cross-ppc64le-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-rx-gcc7-bootstrap.changes b/cross-rx-gcc7-bootstrap.changes
index 101bba7..4da2297 100644
--- a/cross-rx-gcc7-bootstrap.changes
+++ b/cross-rx-gcc7-bootstrap.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-rx-gcc7-bootstrap.spec b/cross-rx-gcc7-bootstrap.spec
index 67ab923..0d56c6f 100644
--- a/cross-rx-gcc7-bootstrap.spec
+++ b/cross-rx-gcc7-bootstrap.spec
@@ -484,6 +484,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-rx-gcc7.changes b/cross-rx-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-rx-gcc7.changes
+++ b/cross-rx-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-rx-gcc7.spec b/cross-rx-gcc7.spec
index c8d9159..c6b158b 100644
--- a/cross-rx-gcc7.spec
+++ b/cross-rx-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-s390x-gcc7.changes b/cross-s390x-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-s390x-gcc7.changes
+++ b/cross-s390x-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-s390x-gcc7.spec b/cross-s390x-gcc7.spec
index d6b8bb3..e78d271 100644
--- a/cross-s390x-gcc7.spec
+++ b/cross-s390x-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-sparc-gcc7.changes b/cross-sparc-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-sparc-gcc7.changes
+++ b/cross-sparc-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-sparc-gcc7.spec b/cross-sparc-gcc7.spec
index 75a1216..07b0422 100644
--- a/cross-sparc-gcc7.spec
+++ b/cross-sparc-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-sparc64-gcc7.changes b/cross-sparc64-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-sparc64-gcc7.changes
+++ b/cross-sparc64-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-sparc64-gcc7.spec b/cross-sparc64-gcc7.spec
index a4deb68..9333f3d 100644
--- a/cross-sparc64-gcc7.spec
+++ b/cross-sparc64-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/cross-x86_64-gcc7.changes b/cross-x86_64-gcc7.changes
index 101bba7..4da2297 100644
--- a/cross-x86_64-gcc7.changes
+++ b/cross-x86_64-gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/cross-x86_64-gcc7.spec b/cross-x86_64-gcc7.spec
index eda16d8..e124a39 100644
--- a/cross-x86_64-gcc7.spec
+++ b/cross-x86_64-gcc7.spec
@@ -483,6 +483,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/gcc.spec.in b/gcc.spec.in
index 383c7b8..d3abb2a 100644
--- a/gcc.spec.in
+++ b/gcc.spec.in
@@ -1274,6 +1274,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/gcc7-testresults.changes b/gcc7-testresults.changes
index 101bba7..4da2297 100644
--- a/gcc7-testresults.changes
+++ b/gcc7-testresults.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/gcc7-testresults.spec b/gcc7-testresults.spec
index 70b2855..b9ba9dd 100644
--- a/gcc7-testresults.spec
+++ b/gcc7-testresults.spec
@@ -660,6 +660,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \
diff --git a/gcc7.changes b/gcc7.changes
index 101bba7..4da2297 100644
--- a/gcc7.changes
+++ b/gcc7.changes
@@ -1,3 +1,8 @@
+-------------------------------------------------------------------
+Tue Apr  3 12:54:54 UTC 2018 - rguenther@suse.com
+
+- Enable --enable-fix-cortex-a53-843419 on aarch64.  [bnc#1084812]
+
 -------------------------------------------------------------------
 Wed Mar  7 08:59:22 UTC 2018 - rguenther@suse.com
 
diff --git a/gcc7.spec b/gcc7.spec
index b948bdb..8ba8ed1 100644
--- a/gcc7.spec
+++ b/gcc7.spec
@@ -1964,6 +1964,9 @@ nvptx-none=%{_prefix}/nvptx-none, \
 	--with-fpu=vfpv3-d16 \
 	--disable-sjlj-exceptions \
 %endif
+%if "%{TARGET_ARCH}" == "aarch64"
+	--enable-fix-cortex-a53-843419 \
+%endif
 %if "%{TARGET_ARCH}" == "powerpc" || "%{TARGET_ARCH}" == "powerpc64" || "%{TARGET_ARCH}" == "powerpc64le"
 %if "%{TARGET_ARCH}" == "powerpc"
         --with-cpu=default32 \