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glibc/ifunc-x86-slow-sse4.patch
Andreas Schwab fe024e3ae1 Accepting request 258649 from home:Andreas_Schwab:Factory 
- Update to crypt_blowfish 1.3.
  * Add support for the $2b$ prefix.
- ifunc-x86-slow-sse4.patch: Fix misdetected Slow_SSE4_2 cpu feature bit
  (BZ #17501)

OBS-URL: https://build.opensuse.org/request/show/258649
OBS-URL: https://build.opensuse.org/package/show/Base:System/glibc?expand=0&rev=389
2014-10-28 11:58:29 +00:00

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2014-10-27 Andreas Schwab <schwab@suse.de>
[BZ #17501]
* sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Fix
check for Slow_SSE4_2 feature bit.
* sysdeps/i386/i686/multiarch/strcmp.S (STRCMP): Likewise.
* sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
* sysdeps/x86_64/multiarch/strcmp.S (STRCMP, __strcascmp):
Likewise. Fix check for Fast_Unaligned_Load feature bit.
Index: glibc-2.20/sysdeps/i386/i686/multiarch/strcasecmp.S
===================================================================
--- glibc-2.20.orig/sysdeps/i386/i686/multiarch/strcasecmp.S
+++ glibc-2.20/sysdeps/i386/i686/multiarch/strcasecmp.S
@@ -37,7 +37,7 @@ ENTRY(__strcasecmp)
leal __strcasecmp_ssse3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f
leal __strcasecmp_sse4_2@GOTOFF(%ebx), %eax
2: popl %ebx
@@ -58,7 +58,7 @@ ENTRY(__strcasecmp)
leal __strcasecmp_ssse3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
+ testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f
leal __strcasecmp_sse4_2, %eax
2: ret
Index: glibc-2.20/sysdeps/i386/i686/multiarch/strcmp.S
===================================================================
--- glibc-2.20.orig/sysdeps/i386/i686/multiarch/strcmp.S
+++ glibc-2.20/sysdeps/i386/i686/multiarch/strcmp.S
@@ -68,7 +68,7 @@ ENTRY(STRCMP)
leal __STRCMP_SSSE3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f
leal __STRCMP_SSE4_2@GOTOFF(%ebx), %eax
2: popl %ebx
@@ -89,7 +89,7 @@ ENTRY(STRCMP)
leal __STRCMP_SSSE3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
+ testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f
leal __STRCMP_SSE4_2, %eax
2: ret
Index: glibc-2.20/sysdeps/i386/i686/multiarch/strncase.S
===================================================================
--- glibc-2.20.orig/sysdeps/i386/i686/multiarch/strncase.S
+++ glibc-2.20/sysdeps/i386/i686/multiarch/strncase.S
@@ -37,7 +37,7 @@ ENTRY(__strncasecmp)
leal __strncasecmp_ssse3@GOTOFF(%ebx), %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
+ testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features@GOTOFF(%ebx)
jnz 2f
leal __strncasecmp_sse4_2@GOTOFF(%ebx), %eax
2: popl %ebx
@@ -58,7 +58,7 @@ ENTRY(__strncasecmp)
leal __strncasecmp_ssse3, %eax
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
- testl $bit_Slow_SSE4_2, CPUID_OFFSET+index_Slow_SSE4_2+__cpu_features
+ testl $bit_Slow_SSE4_2, FEATURE_OFFSET+index_Slow_SSE4_2+__cpu_features
jnz 2f
leal __strncasecmp_sse4_2, %eax
2: ret
Index: glibc-2.20/sysdeps/x86_64/multiarch/strcmp.S
===================================================================
--- glibc-2.20.orig/sysdeps/x86_64/multiarch/strcmp.S
+++ glibc-2.20/sysdeps/x86_64/multiarch/strcmp.S
@@ -91,10 +91,10 @@ ENTRY(STRCMP)
1:
#ifdef USE_AS_STRCMP
leaq __strcmp_sse2_unaligned(%rip), %rax
- testl $bit_Fast_Unaligned_Load, __cpu_features+CPUID_OFFSET+index_Fast_Unaligned_Load(%rip)
+ testl $bit_Fast_Unaligned_Load, __cpu_features+FEATURE_OFFSET+index_Fast_Unaligned_Load(%rip)
jnz 3f
#else
- testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
+ testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
jnz 2f
leaq STRCMP_SSE42(%rip), %rax
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
@@ -120,7 +120,7 @@ ENTRY(__strcasecmp)
testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
jnz 3f
# endif
- testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
+ testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
jnz 2f
leaq __strcasecmp_sse42(%rip), %rax
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
@@ -146,7 +146,7 @@ ENTRY(__strncasecmp)
testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
jnz 3f
# endif
- testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
+ testl $bit_Slow_SSE4_2, __cpu_features+FEATURE_OFFSET+index_Slow_SSE4_2(%rip)
jnz 2f
leaq __strncasecmp_sse42(%rip), %rax
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
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