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Accepting request 502898 from home:pluskalm:branches:devel:libraries:c_c++

Browse Source 
- Update to version 1.20:
- Package command line utils as well

old: devel:libraries:c_c++/leveldb
new: home:pluskalm:branches:devel:libraries:c_c++/leveldb rev None
Index: leveldb.changes
===================================================================
--- leveldb.changes (revision 17)
+++ leveldb.changes (revision 3)
@@ -1,4 +1,49 @@
 -------------------------------------------------------------------
+Sun Jun 11 17:07:36 UTC 2017 - mpluskal@suse.com
+
+- Update to version 1.20:
+  * Convert documentation to markdown.
+  * Implement support for Intel crc32 instruction (SSE 4.2).
+  * Limit the number of read-only files the POSIX Env will have
+    open.
+  * Add option for maximum file size.
+- Changes for version 1.19:
+  * A snappy change broke test assumptions about the size of
+    compressed output.
+  * Fix problems in LevelDB's caching code.
+  * Fix LevelDB build when asserts are enabled in release builds.
+  * Change std::uint64_t to uint64_t (#354).
+  * Fixes a bug encountered when reading records from leveldb
+    files that have
+  * been split, as in a [] input task split.
+  * Deleted redundant null ptr check prior to delete. (#338).
+  * Fix signed/unsigned mismatch on VC++ builds.
+  * Putting build artifacts in subdirectory.
+  * Added continuous build integration via Travis CI.
+  * log compaction output file's level along with number.
+  * Misc. improvements to README file.
+  * Fix Android/MIPS build (#115).
+  * Only compiling TrimSpace on linux (#310).
+  * Use xcrun to determine Xcode.app path instead of using a
+    hardcoded path.
+  * Add "approximate-memory-usage" property to
+    leveldb::DB::GetProperty.
+  * Addleveldb::Cache::Prune.
+  * Fix size_t/int comparison/conversion issues.
+  * Added leveldb::Status::IsInvalidArgument() method.
+  * Suppress error reporting after seeking but before a valid First
+    or Full record is encountered.
+  * #include -> (#280).
+  * Now attempts to reuse the preceding MANIFEST and log file when
+    re-opened.
+  * Add benchmark that measures cost of repeatedly opening the
+    database.
+  * Added a new fault injection test.
+  * Add arm64 support to leveldb.
+- Drop no longer needed 0001-debian-ports.patch
+- Package command line utils as well
+
+-------------------------------------------------------------------
 Sun Apr  5 13:29:58 UTC 2015 - mpluskal@suse.com
 
 - Update project url
Index: leveldb.spec
===================================================================
--- leveldb.spec (revision 17)
+++ leveldb.spec (revision 3)
@@ -1,7 +1,7 @@
 #
 # spec file for package leveldb
 #
-# Copyright (c) 2015 SUSE LINUX GmbH, Nuernberg, Germany.
+# Copyright (c) 2017 SUSE LINUX GmbH, Nuernberg, Germany.
 #
 # All modifications and additions to the file contributed by third parties
 # remain the property of their copyright owners, unless otherwise agreed
@@ -17,17 +17,15 @@
 
 
 Name:           leveldb
-Version:        1.18
+Version:        1.20
 Release:        0
 Summary:        A key/value-store
 License:        BSD-3-Clause
 Group:          Development/Libraries/C and C++
 Url:            https://github.com/google/leveldb
-Source0:        https://github.com/google/leveldb/archive/v%{version}.tar.gz
-Patch0:         0001-debian-ports.patch
+Source0:        https://github.com/google/leveldb/archive/v%{version}.tar.gz#/%{name}-%{version}.tar.gz
 BuildRequires:  gcc-c++
 BuildRequires:  snappy-devel
-BuildRoot:      %{_tmppath}/%{name}-%{version}-build
 
 %description
 leveldb implements a system for maintaining a persistent key/value store.
@@ -67,38 +65,47 @@
 
 %prep
 %setup -q
-%patch0 -p1
 
 %build
 make %{?_smp_mflags} OPT="%{optflags}"
 
-%check
-make %{?_smp_mflags} check
-
 %install
-install -d -m 0755 %{buildroot}%{_includedir} %{buildroot}%{_libdir}
+install -d -m 0755 \
+  %{buildroot}%{_includedir} \
+  %{buildroot}%{_libdir} \
+  %{buildroot}%{_bindir}
 
 cp -a \
-    libleveldb.a   \
-    libleveldb.so* \
+  out-static/libleveldb.a   \
+  out-shared/libleveldb.so* \
   %{buildroot}%{_libdir}
 
-cp -a include/leveldb   %{buildroot}%{_includedir}
-find %{buildroot} -type f -name "*.la" -delete -print
+cp -a include/leveldb \
+  %{buildroot}%{_includedir}
 
-%post   -n %{lib_name} -p /sbin/ldconfig
+cp -a \
+  out-shared/db_bench \
+  %{buildroot}%{_bindir}
 
+%check
+make %{?_smp_mflags} check
+
+%post   -n %{lib_name} -p /sbin/ldconfig
 %postun -n %{lib_name} -p /sbin/ldconfig
 
+%files
+%defattr(-,root,root,-)
+%{_bindir}/db_bench
+
 %files -n %{lib_name}
 %defattr(-,root,root,-)
 %{_libdir}/libleveldb.so.*
 
 %files devel
 %defattr(-,root,root,-)
-%{_libdir}/libleveldb.so
+%doc AUTHORS LICENSE NEWS README.md TODO doc/*
 %{_includedir}/leveldb/
-%doc AUTHORS LICENSE NEWS README TODO doc/*
+%{_libdir}/libleveldb.so
 
 %files devel-static
 %defattr(-,root,root,-)
Index: leveldb-1.20.tar.gz
===================================================================
Binary file leveldb-1.20.tar.gz (revision 3) added
Index: 0001-debian-ports.patch
===================================================================
--- 0001-debian-ports.patch (revision 17)
+++ 0001-debian-ports.patch (deleted)
@@ -1,205 +0,0 @@
-Description: Add support for most of Debian architectures
-Author: Nobuhiro Iwamatsu <iwamatsu@debian.org>
----
- port/atomic_pointer.h |  136 ++++++++++++++++++++++++++++++++++++++++++++++----
- 1 file changed, 126 insertions(+), 10 deletions(-)
-
-Index: leveldb-1.18/port/atomic_pointer.h
-===================================================================
---- leveldb-1.18.orig/port/atomic_pointer.h
-+++ leveldb-1.18/port/atomic_pointer.h
-@@ -37,6 +37,18 @@
- #define ARCH_CPU_ARM_FAMILY 1
- #elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
- #define ARCH_CPU_PPC_FAMILY 1
-+#elif defined(__ia64__)
-+#define ARCH_CPU_IA64_FAMILY 1
-+#elif defined(__alpha__)
-+#define ARCH_CPU_ALPHA_FAMILY 1
-+#elif defined(__s390x__) || defined(__s390__)
-+#define ARCH_CPU_S390_FAMILY 1
-+#elif defined(__sparc__) || defined(__sparc64__)
-+#define ARCH_CPU_SPARC_FAMILY 1
-+#elif defined(__sh__)
-+#define ARCH_CPU_SH_FAMILY 1
-+#elif defined(__hppa__) || defined(__parisc__)
-+#define ARCH_CPU_PARISC_FAMILY 1
- #endif
- 
- namespace leveldb {
-@@ -49,16 +61,27 @@ namespace port {
- // http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
-+#define ReadMemoryBarrier MemoryBarrier()
-+#define WriteMemoryBarrier MemoryBarrier()
-+
- // Mac OS
- #elif defined(OS_MACOSX)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  OSMemoryBarrier();
-+}
-+inline void WriteMemoryBarrier() {
-   OSMemoryBarrier();
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
- // Gcc on x86
- #elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-+  // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-   // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-   // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-   __asm__ __volatile__("" : : : "memory");
-@@ -67,7 +90,12 @@ inline void MemoryBarrier() {
- 
- // Sun Studio
- #elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-+  // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-+  asm volatile("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-   // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-   // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-   asm volatile("" : : : "memory");
-@@ -87,17 +115,99 @@ typedef void (*LinuxKernelMemoryBarrierF
- // shows that the extra function call cost is completely negligible on
- // multi-core devices.
- //
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
-+}
-+inline void WriteMemoryBarrier() {
-   (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
- // PPC
- #elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
--inline void MemoryBarrier() {
--  // TODO for some powerpc expert: is there a cheaper suitable variant?
--  // Perhaps by having separate barriers for acquire and release ops.
--  asm volatile("sync" : : : "memory");
-+
-+inline void ReadMemoryBarrier() {
-+#ifdef __powerpc64__
-+  __asm__ __volatile__ ("lwsync" : : : "memory");
-+#else
-+  __asm__ __volatile__ ("sync" : : : "memory");
-+#endif
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("sync" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// IA64
-+#elif defined(ARCH_CPU_IA64_FAMILY)
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__ ("mf" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("mf" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// ALPHA
-+#elif defined(ARCH_CPU_ALPHA_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__("mb" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__("wmb" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// S390
-+#elif defined(ARCH_CPU_S390_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  asm volatile("bcr 15,0" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  asm volatile("bcr 15,0" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// SPARC
-+#elif defined(ARCH_CPU_SPARC_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// SH
-+#elif defined(ARCH_CPU_SH_FAMILY)
-+#if defined(__SH4A__) || defined(__SH5__)
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__ ("synco": : :"memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("synco": : :"memory");
-+}
-+#else
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__ ("": : :"memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("": : :"memory");
-+}
-+#endif
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// PARISC
-+#elif defined(ARCH_CPU_PARISC_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory")
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory")
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
-@@ -115,11 +225,11 @@ class AtomicPointer {
-   inline void NoBarrier_Store(void* v) { rep_ = v; }
-   inline void* Acquire_Load() const {
-     void* result = rep_;
--    MemoryBarrier();
-+    ReadMemoryBarrier();
-     return result;
-   }
-   inline void Release_Store(void* v) {
--    MemoryBarrier();
-+    WriteMemoryBarrier();
-     rep_ = v;
-   }
- };
-@@ -216,6 +326,12 @@ class AtomicPointer {
- #undef ARCH_CPU_X86_FAMILY
- #undef ARCH_CPU_ARM_FAMILY
- #undef ARCH_CPU_PPC_FAMILY
-+#undef ARCH_CPU_IA64_FAMILY
-+#undef ARCH_CPU_ALPHA_FAMILY
-+#undef ARCH_CPU_S390_FAMILY
-+#undef ARCH_CPU_SPARC_FAMILY
-+#undef ARCH_CPU_SH_FAMILY
-+#undef ARCH_CPU_PARISC_FAMILY
- 
- }  // namespace port
- }  // namespace leveldb
Index: v1.18.tar.gz
===================================================================
Binary file v1.18.tar.gz (revision 17) deleted

OBS-URL: https://build.opensuse.org/request/show/502898
OBS-URL: https://build.opensuse.org/package/show/devel:libraries:c_c++/leveldb?expand=0&rev=18
This commit is contained in:
Adam Majer 2017-06-14 12:00:48 +00:00 committed by Git OBS Bridge
parent af654968fa
commit 68e280c558
5 changed files with 75 additions and 228 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

205
0001-debian-ports.patch
View File

@ -1,205 +0,0 @@
Description: Add support for most of Debian architectures
Author: Nobuhiro Iwamatsu <iwamatsu@debian.org>
---
port/atomic_pointer.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 126 insertions(+), 10 deletions(-)
Index: leveldb-1.18/port/atomic_pointer.h
===================================================================
--- leveldb-1.18.orig/port/atomic_pointer.h
+++ leveldb-1.18/port/atomic_pointer.h
@@ -37,6 +37,18 @@
#define ARCH_CPU_ARM_FAMILY 1
#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
#define ARCH_CPU_PPC_FAMILY 1
+#elif defined(__ia64__)
+#define ARCH_CPU_IA64_FAMILY 1
+#elif defined(__alpha__)
+#define ARCH_CPU_ALPHA_FAMILY 1
+#elif defined(__s390x__) || defined(__s390__)
+#define ARCH_CPU_S390_FAMILY 1
+#elif defined(__sparc__) || defined(__sparc64__)
+#define ARCH_CPU_SPARC_FAMILY 1
+#elif defined(__sh__)
+#define ARCH_CPU_SH_FAMILY 1
+#elif defined(__hppa__) || defined(__parisc__)
+#define ARCH_CPU_PARISC_FAMILY 1
#endif
namespace leveldb {
@@ -49,16 +61,27 @@ namespace port {
// http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx
#define LEVELDB_HAVE_MEMORY_BARRIER
+#define ReadMemoryBarrier MemoryBarrier()
+#define WriteMemoryBarrier MemoryBarrier()
+
// Mac OS
#elif defined(OS_MACOSX)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ OSMemoryBarrier();
+}
+inline void WriteMemoryBarrier() {
OSMemoryBarrier();
}
#define LEVELDB_HAVE_MEMORY_BARRIER
// Gcc on x86
#elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
__asm__ __volatile__("" : : : "memory");
@@ -67,7 +90,12 @@ inline void MemoryBarrier() {
// Sun Studio
#elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
+ asm volatile("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
asm volatile("" : : : "memory");
@@ -87,17 +115,99 @@ typedef void (*LinuxKernelMemoryBarrierF
// shows that the extra function call cost is completely negligible on
// multi-core devices.
//
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
+}
+inline void WriteMemoryBarrier() {
(*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
}
#define LEVELDB_HAVE_MEMORY_BARRIER
// PPC
#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
-inline void MemoryBarrier() {
- // TODO for some powerpc expert: is there a cheaper suitable variant?
- // Perhaps by having separate barriers for acquire and release ops.
- asm volatile("sync" : : : "memory");
+
+inline void ReadMemoryBarrier() {
+#ifdef __powerpc64__
+ __asm__ __volatile__ ("lwsync" : : : "memory");
+#else
+ __asm__ __volatile__ ("sync" : : : "memory");
+#endif
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// IA64
+#elif defined(ARCH_CPU_IA64_FAMILY)
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("mf" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("mf" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// ALPHA
+#elif defined(ARCH_CPU_ALPHA_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("mb" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("wmb" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// S390
+#elif defined(ARCH_CPU_S390_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ asm volatile("bcr 15,0" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ asm volatile("bcr 15,0" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// SPARC
+#elif defined(ARCH_CPU_SPARC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// SH
+#elif defined(ARCH_CPU_SH_FAMILY)
+#if defined(__SH4A__) || defined(__SH5__)
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+#else
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("": : :"memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("": : :"memory");
+}
+#endif
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// PARISC
+#elif defined(ARCH_CPU_PARISC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory")
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory")
}
#define LEVELDB_HAVE_MEMORY_BARRIER
@@ -115,11 +225,11 @@ class AtomicPointer {
inline void NoBarrier_Store(void* v) { rep_ = v; }
inline void* Acquire_Load() const {
void* result = rep_;
- MemoryBarrier();
+ ReadMemoryBarrier();
return result;
}
inline void Release_Store(void* v) {
- MemoryBarrier();
+ WriteMemoryBarrier();
rep_ = v;
}
};
@@ -216,6 +326,12 @@ class AtomicPointer {
#undef ARCH_CPU_X86_FAMILY
#undef ARCH_CPU_ARM_FAMILY
#undef ARCH_CPU_PPC_FAMILY
+#undef ARCH_CPU_IA64_FAMILY
+#undef ARCH_CPU_ALPHA_FAMILY
+#undef ARCH_CPU_S390_FAMILY
+#undef ARCH_CPU_SPARC_FAMILY
+#undef ARCH_CPU_SH_FAMILY
+#undef ARCH_CPU_PARISC_FAMILY
} // namespace port
} // namespace leveldb

3
leveldb-1.20.tar.gz Normal file
View File

@ -0,0 +1,3 @@
version https://git-lfs.github.com/spec/v1
oid sha256:f5abe8b5b209c2f36560b75f32ce61412f39a2922f7045ae764a2c23335b6664
size 223141

45
leveldb.changes
View File

@ -1,3 +1,48 @@
-------------------------------------------------------------------
Sun Jun 11 17:07:36 UTC 2017 - mpluskal@suse.com
- Update to version 1.20:
* Convert documentation to markdown.
* Implement support for Intel crc32 instruction (SSE 4.2).
* Limit the number of read-only files the POSIX Env will have
open.
* Add option for maximum file size.
- Changes for version 1.19:
* A snappy change broke test assumptions about the size of
compressed output.
* Fix problems in LevelDB's caching code.
* Fix LevelDB build when asserts are enabled in release builds.
* Change std::uint64_t to uint64_t (#354).
* Fixes a bug encountered when reading records from leveldb
files that have
* been split, as in a [] input task split.
* Deleted redundant null ptr check prior to delete. (#338).
* Fix signed/unsigned mismatch on VC++ builds.
* Putting build artifacts in subdirectory.
* Added continuous build integration via Travis CI.
* log compaction output file's level along with number.
* Misc. improvements to README file.
* Fix Android/MIPS build (#115).
* Only compiling TrimSpace on linux (#310).
* Use xcrun to determine Xcode.app path instead of using a
hardcoded path.
* Add "approximate-memory-usage" property to
leveldb::DB::GetProperty.
* Addleveldb::Cache::Prune.
* Fix size_t/int comparison/conversion issues.
* Added leveldb::Status::IsInvalidArgument() method.
* Suppress error reporting after seeking but before a valid First
or Full record is encountered.
* #include -> (#280).
* Now attempts to reuse the preceding MANIFEST and log file when
re-opened.
* Add benchmark that measures cost of repeatedly opening the
database.
* Added a new fault injection test.
* Add arm64 support to leveldb.
- Drop no longer needed 0001-debian-ports.patch
- Package command line utils as well
-------------------------------------------------------------------
Sun Apr 5 13:29:58 UTC 2015 - mpluskal@suse.com

47
leveldb.spec
View File

@ -1,7 +1,7 @@
#
# spec file for package leveldb
#
# Copyright (c) 2015 SUSE LINUX GmbH, Nuernberg, Germany.
# Copyright (c) 2017 SUSE LINUX GmbH, Nuernberg, Germany.
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
@ -17,17 +17,15 @@
Name: leveldb
Version: 1.18
Version: 1.20
Release: 0
Summary: A key/value-store
License: BSD-3-Clause
Group: Development/Libraries/C and C++
Url: https://github.com/google/leveldb
Source0: https://github.com/google/leveldb/archive/v%{version}.tar.gz
Patch0: 0001-debian-ports.patch
Source0: https://github.com/google/leveldb/archive/v%{version}.tar.gz#/%{name}-%{version}.tar.gz
BuildRequires: gcc-c++
BuildRequires: snappy-devel
BuildRoot: %{_tmppath}/%{name}-%{version}-build
%description
leveldb implements a system for maintaining a persistent key/value store.
@ -67,38 +65,47 @@ This package holds the development files for statically linking leveldb.
%prep
%setup -q
%patch0 -p1
%build
make %{?_smp_mflags} OPT="%{optflags}"
%install
install -d -m 0755 \
%{buildroot}%{_includedir} \
%{buildroot}%{_libdir} \
%{buildroot}%{_bindir}
cp -a \
out-static/libleveldb.a \
out-shared/libleveldb.so* \
%{buildroot}%{_libdir}
cp -a include/leveldb \
%{buildroot}%{_includedir}
cp -a \
out-shared/db_bench \
%{buildroot}%{_bindir}
%check
make %{?_smp_mflags} check
%install
install -d -m 0755 %{buildroot}%{_includedir} %{buildroot}%{_libdir}
cp -a \
libleveldb.a \
libleveldb.so* \
%{buildroot}%{_libdir}
cp -a include/leveldb %{buildroot}%{_includedir}
find %{buildroot} -type f -name "*.la" -delete -print
%post -n %{lib_name} -p /sbin/ldconfig
%postun -n %{lib_name} -p /sbin/ldconfig
%files
%defattr(-,root,root,-)
%{_bindir}/db_bench
%files -n %{lib_name}
%defattr(-,root,root,-)
%{_libdir}/libleveldb.so.*
%files devel
%defattr(-,root,root,-)
%{_libdir}/libleveldb.so
%doc AUTHORS LICENSE NEWS README.md TODO doc/*
%{_includedir}/leveldb/
%doc AUTHORS LICENSE NEWS README TODO doc/*
%{_libdir}/libleveldb.so
%files devel-static
%defattr(-,root,root,-)

3
v1.18.tar.gz
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@ -1,3 +0,0 @@
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oid sha256:4aa1a7479bc567b95a59ac6fb79eba49f61884d6fd400f20b7af147d54c5cee5
size 209376