Accepting request 212331 from devel:libraries:c_c++
Automatic submission by obs-autosubmit OBS-URL: https://build.opensuse.org/request/show/212331 OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/leveldb?expand=0&rev=2
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Stephan Kulow
Git OBS Bridge
commit
d4d828b982
204
0001-debian-ports.patch
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204
0001-debian-ports.patch
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@ -0,0 +1,204 @@
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Description: Add support for most of Debian architectures
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Author: Nobuhiro Iwamatsu <iwamatsu@debian.org>
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---
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port/atomic_pointer.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++----
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1 file changed, 126 insertions(+), 10 deletions(-)
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--- leveldb.orig/port/atomic_pointer.h
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+++ leveldb/port/atomic_pointer.h
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@@ -38,6 +38,18 @@
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#define ARCH_CPU_ARM_FAMILY 1
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#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
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#define ARCH_CPU_PPC_FAMILY 1
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+#elif defined(__ia64__)
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+#define ARCH_CPU_IA64_FAMILY 1
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+#elif defined(__alpha__)
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+#define ARCH_CPU_ALPHA_FAMILY 1
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+#elif defined(__s390x__) || defined(__s390__)
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+#define ARCH_CPU_S390_FAMILY 1
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+#elif defined(__sparc__) || defined(__sparc64__)
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+#define ARCH_CPU_SPARC_FAMILY 1
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+#elif defined(__sh__)
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+#define ARCH_CPU_SH_FAMILY 1
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+#elif defined(__hppa__) || defined(__parisc__)
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+#define ARCH_CPU_PARISC_FAMILY 1
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#endif
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namespace leveldb {
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@@ -50,9 +62,17 @@ namespace port {
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// http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx
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#define LEVELDB_HAVE_MEMORY_BARRIER
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+#define ReadMemoryBarrier MemoryBarrier()
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+#define WriteMemoryBarrier MemoryBarrier()
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+
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// Gcc on x86
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#elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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__asm__ __volatile__("" : : : "memory");
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@@ -61,7 +81,12 @@ inline void MemoryBarrier() {
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// Sun Studio
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#elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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+ asm volatile("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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asm volatile("" : : : "memory");
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@@ -70,7 +95,10 @@ inline void MemoryBarrier() {
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// Mac OS
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#elif defined(OS_MACOSX)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ OSMemoryBarrier();
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+}
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+inline void WriteMemoryBarrier() {
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OSMemoryBarrier();
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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@@ -88,17 +116,99 @@ typedef void (*LinuxKernelMemoryBarrierF
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// shows that the extra function call cost is completely negligible on
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// multi-core devices.
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//
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
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+}
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+inline void WriteMemoryBarrier() {
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(*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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// PPC
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#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
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-inline void MemoryBarrier() {
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- // TODO for some powerpc expert: is there a cheaper suitable variant?
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- // Perhaps by having separate barriers for acquire and release ops.
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- asm volatile("sync" : : : "memory");
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+
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+inline void ReadMemoryBarrier() {
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+#ifdef __powerpc64__
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+ __asm__ __volatile__ ("lwsync" : : : "memory");
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+#else
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+ __asm__ __volatile__ ("sync" : : : "memory");
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+#endif
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("sync" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// IA64
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+#elif defined(ARCH_CPU_IA64_FAMILY)
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__ ("mf" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("mf" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// ALPHA
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+#elif defined(ARCH_CPU_ALPHA_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__("mb" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__("wmb" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// S390
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+#elif defined(ARCH_CPU_S390_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ asm volatile("bcr 15,0" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ asm volatile("bcr 15,0" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// SPARC
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+#elif defined(ARCH_CPU_SPARC_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// SH
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+#elif defined(ARCH_CPU_SH_FAMILY)
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+#if defined(__SH4A__) || defined(__SH5__)
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__ ("synco": : :"memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("synco": : :"memory");
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+}
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+#else
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__ ("": : :"memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("": : :"memory");
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+}
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+#endif
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// PARISC
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+#elif defined(ARCH_CPU_PARISC_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory")
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory")
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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@@ -116,11 +226,11 @@ class AtomicPointer {
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inline void NoBarrier_Store(void* v) { rep_ = v; }
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inline void* Acquire_Load() const {
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void* result = rep_;
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- MemoryBarrier();
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+ ReadMemoryBarrier();
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return result;
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}
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inline void Release_Store(void* v) {
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- MemoryBarrier();
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+ WriteMemoryBarrier();
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rep_ = v;
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}
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};
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@@ -217,6 +327,12 @@ class AtomicPointer {
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#undef ARCH_CPU_X86_FAMILY
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#undef ARCH_CPU_ARM_FAMILY
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#undef ARCH_CPU_PPC_FAMILY
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+#undef ARCH_CPU_IA64_FAMILY
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+#undef ARCH_CPU_ALPHA_FAMILY
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+#undef ARCH_CPU_S390_FAMILY
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+#undef ARCH_CPU_SPARC_FAMILY
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+#undef ARCH_CPU_SH_FAMILY
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+#undef ARCH_CPU_PARISC_FAMILY
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} // namespace port
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} // namespace leveldb
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@ -1,3 +1,8 @@
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-------------------------------------------------------------------
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Wed Dec 18 17:49:35 CET 2013 - ro@suse.de
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- add support for other archs (taken from debian, 0001-debian-ports.patch)
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-------------------------------------------------------------------
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Sun Nov 3 22:51:28 UTC 2013 - ddiss@suse.com
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10
leveldb.spec
10
leveldb.spec
@ -19,11 +19,12 @@
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Name: leveldb
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Version: 1.14.0
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Release: 0
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License: BSD-3-Clause
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Summary: A key/value-store
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Url: http://code.google.com/p/leveldb/
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License: BSD-3-Clause
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Group: Development/Libraries/C and C++
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Url: http://code.google.com/p/leveldb/
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Source: leveldb-%{version}.tar.gz
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Patch0: 0001-debian-ports.patch
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BuildRequires: gcc-c++
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BuildRequires: snappy-devel
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BuildRoot: %{_tmppath}/%{name}-%{version}-build
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@ -35,8 +36,8 @@ leveldb implements a system for maintaining a persistent key/value store.
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%package -n %{lib_name}
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Summary: Shared library from leveldb
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Group: System/Libraries
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Provides: %{name} = %{version}
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Obsoletes: %{name} < %{version}
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Provides: %{name} = %{version}
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Obsoletes: %{name} < %{version}
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%description -n %{lib_name}
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leveldb implements a system for maintaining a persistent key/value store.
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@ -65,6 +66,7 @@ This package holds the development files for statically linking leveldb.
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%prep
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%setup -q
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%patch0 -p1
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%build
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make %{?_smp_flags} OPT="%{optflags}"
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