diff --git a/0001-debian-ports.patch b/0001-debian-ports.patch
deleted file mode 100644
index 38460c5..0000000
--- a/0001-debian-ports.patch
+++ /dev/null
@@ -1,208 +0,0 @@
-diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
-index 1c4c7aa..c2c34b1 100644
---- a/port/atomic_pointer.h
-+++ b/port/atomic_pointer.h
-@@ -41,6 +41,18 @@
- #define ARCH_CPU_PPC_FAMILY 1
- #elif defined(__mips__)
- #define ARCH_CPU_MIPS_FAMILY 1
-+#elif defined(__ia64__)
-+#define ARCH_CPU_IA64_FAMILY 1
-+#elif defined(__alpha__)
-+#define ARCH_CPU_ALPHA_FAMILY 1
-+#elif defined(__s390x__) || defined(__s390__)
-+#define ARCH_CPU_S390_FAMILY 1
-+#elif defined(__sparc__) || defined(__sparc64__)
-+#define ARCH_CPU_SPARC_FAMILY 1
-+#elif defined(__sh__)
-+#define ARCH_CPU_SH_FAMILY 1
-+#elif defined(__hppa__) || defined(__parisc__)
-+#define ARCH_CPU_PARISC_FAMILY 1
- #endif
- 
- namespace leveldb {
-@@ -55,14 +67,25 @@ namespace port {
- 
- // Mac OS
- #elif defined(OS_MACOSX)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  OSMemoryBarrier();
-+}
-+inline void WriteMemoryBarrier() {
-   OSMemoryBarrier();
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
-+#define ReadMemoryBarrier MemoryBarrier()
-+#define WriteMemoryBarrier MemoryBarrier()
-+
- // Gcc on x86
- #elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-+  // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-   // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-   // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-   __asm__ __volatile__("" : : : "memory");
-@@ -71,7 +94,12 @@ inline void MemoryBarrier() {
- 
- // Sun Studio
- #elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-+  // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-+  asm volatile("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-   // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
-   // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
-   asm volatile("" : : : "memory");
-@@ -91,24 +119,109 @@ typedef void (*LinuxKernelMemoryBarrierFunc)(void);
- // shows that the extra function call cost is completely negligible on
- // multi-core devices.
- //
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
-+}
-+inline void WriteMemoryBarrier() {
-   (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
- // ARM64
- #elif defined(ARCH_CPU_ARM64_FAMILY)
--inline void MemoryBarrier() {
-+inline void ReadMemoryBarrier() {
-+  asm volatile("dmb sy" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-   asm volatile("dmb sy" : : : "memory");
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
- // PPC
- #elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
--inline void MemoryBarrier() {
--  // TODO for some powerpc expert: is there a cheaper suitable variant?
--  // Perhaps by having separate barriers for acquire and release ops.
--  asm volatile("sync" : : : "memory");
-+
-+inline void ReadMemoryBarrier() {
-+#ifdef __powerpc64__
-+  __asm__ __volatile__ ("lwsync" : : : "memory");
-+#else
-+  __asm__ __volatile__ ("sync" : : : "memory");
-+#endif
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("sync" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// IA64
-+#elif defined(ARCH_CPU_IA64_FAMILY)
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__ ("mf" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("mf" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// ALPHA
-+#elif defined(ARCH_CPU_ALPHA_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__("mb" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__("wmb" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// S390
-+#elif defined(ARCH_CPU_S390_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  asm volatile("bcr 15,0" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  asm volatile("bcr 15,0" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// SPARC
-+#elif defined(ARCH_CPU_SPARC_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// SH
-+#elif defined(ARCH_CPU_SH_FAMILY)
-+#if defined(__SH4A__) || defined(__SH5__)
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__ ("synco": : :"memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("synco": : :"memory");
-+}
-+#else
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__ ("": : :"memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__ ("": : :"memory");
-+}
-+#endif
-+#define LEVELDB_HAVE_MEMORY_BARRIER
-+
-+// PARISC
-+#elif defined(ARCH_CPU_PARISC_FAMILY)
-+
-+inline void ReadMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory");
-+}
-+inline void WriteMemoryBarrier() {
-+  __asm__ __volatile__("" : : : "memory");
- }
- #define LEVELDB_HAVE_MEMORY_BARRIER
- 
-@@ -133,11 +246,11 @@ class AtomicPointer {
-   inline void NoBarrier_Store(void* v) { rep_ = v; }
-   inline void* Acquire_Load() const {
-     void* result = rep_;
--    MemoryBarrier();
-+    ReadMemoryBarrier();
-     return result;
-   }
-   inline void Release_Store(void* v) {
--    MemoryBarrier();
-+    WriteMemoryBarrier();
-     rep_ = v;
-   }
- };
-@@ -235,6 +348,12 @@ class AtomicPointer {
- #undef ARCH_CPU_ARM_FAMILY
- #undef ARCH_CPU_ARM64_FAMILY
- #undef ARCH_CPU_PPC_FAMILY
-+#undef ARCH_CPU_IA64_FAMILY
-+#undef ARCH_CPU_ALPHA_FAMILY
-+#undef ARCH_CPU_S390_FAMILY
-+#undef ARCH_CPU_SPARC_FAMILY
-+#undef ARCH_CPU_SH_FAMILY
-+#undef ARCH_CPU_PARISC_FAMILY
- 
- }  // namespace port
- }  // namespace leveldb
diff --git a/leveldb-1.20.tar.gz b/leveldb-1.20.tar.gz
deleted file mode 100644
index fffc9e3..0000000
--- a/leveldb-1.20.tar.gz
+++ /dev/null
@@ -1,3 +0,0 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:f5abe8b5b209c2f36560b75f32ce61412f39a2922f7045ae764a2c23335b6664
-size 223141
diff --git a/leveldb-1.22.tar.gz b/leveldb-1.22.tar.gz
new file mode 100644
index 0000000..8936732
--- /dev/null
+++ b/leveldb-1.22.tar.gz
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:55423cac9e3306f4a9502c738a001e4a339d1a38ffbee7572d4a07d5d63949b2
+size 239365
diff --git a/leveldb.changes b/leveldb.changes
index 32d0e56..2b703a0 100644
--- a/leveldb.changes
+++ b/leveldb.changes
@@ -1,3 +1,47 @@
+-------------------------------------------------------------------
+Wed Apr 29 12:33:36 UTC 2020 - David Disseldorp <ddiss@suse.com>
+
+- Remove 0001-debian-ports.patch
+  * std::atomic now used instead of internal AtomicPointer asm
+- Update to version 1.22:
+  * Corrected formatting to be compliant with the Google C++ Style Guide.
+  * Restore soname versioning with CMake build.
+  * Other miscellaneous cleanups, fixes, and improvements.
+- Update to version 1.21:
+  * Add tests for empty keys and values.
+  * Switch corruption_test to use InMemEnv.
+  * Replace AtomicPointer with std::atomic.
+  * Make InMemoryEnv more consistent with filesystem based Env's.
+  * Align windows_logger with posix_logger.
+  * Added native support for Windows.
+  * Make WriteBatch::ApproximateSize() const.
+  * Fix fdatasync() feature detection in opensource build.
+  * C++11 cleanup for util/mutexlock.h.
+  * Rework threading in env_posix.cc.
+  * Remove InitOnce from the port API.
+  * Expose WriteBatch::Append().
+  * Fix documentation for log file growth.
+  * Add move constructor to Status.
+  * Replace port_posix with port_stdcxx.
+  * Reimplement ConsumeDecimalNumber.
+  * Replace NULL with nullptr in C++ files.
+  * Remove PLATFORM_IS_LITTLE_ENDIAN from port/posix.h.
+  * Add more thread safety annotations.
+  * Require C++11.
+  * Replace SIZE_MAX with std::numeric_limits.
+  * Add CMake build support.
+  * Enable thread safety annotations.
+  * leveldb::DestroyDB will now delete empty directories.
+  * Replace SSE-optimized CRC32C in POSIX port with external library.
+  * Fix file writing bug in CL 170738066.
+  * Fix use of uninitialized value in LRUHandle.
+  * Fix issue #474: a race between the f*_unlocked() STDIO calls in
+    env_posix.cc and concurrent application calls to fflush(NULL).
+  * Report missing CURRENT manifest file as database corruption.
+  * LevelDB: Add WriteBatch::ApproximateSize().
+  * Other minor fixes, code cleanup, and documentation improvements.
+- Perform a two-pass build, once for static and once for shared libs
+
 -------------------------------------------------------------------
 Fri Aug  2 07:04:04 UTC 2019 - Martin Liška <mliska@suse.cz>
 
diff --git a/leveldb.spec b/leveldb.spec
index 5244b16..8e18ce7 100644
--- a/leveldb.spec
+++ b/leveldb.spec
@@ -1,7 +1,7 @@
 #
 # spec file for package leveldb
 #
-# Copyright (c) 2019 SUSE LINUX GmbH, Nuernberg, Germany.
+# Copyright (c) 2020 SUSE LLC
 #
 # All modifications and additions to the file contributed by third parties
 # remain the property of their copyright owners, unless otherwise agreed
@@ -17,14 +17,14 @@
 
 
 Name:           leveldb
-Version:        1.20
+Version:        1.22
 Release:        0
 Summary:        A key/value-store
 License:        BSD-3-Clause
 Group:          Development/Libraries/C and C++
-Url:            https://github.com/google/leveldb
-Source0:        https://github.com/google/leveldb/archive/v%{version}.tar.gz#/%{name}-%{version}.tar.gz
-Patch0:         0001-debian-ports.patch
+URL:            https://github.com/google/leveldb
+Source0:        https://github.com/google/leveldb/archive/%{version}.tar.gz#/%{name}-%{version}.tar.gz
+BuildRequires:  cmake
 BuildRequires:  gcc-c++
 BuildRequires:  snappy-devel
 
@@ -66,32 +66,26 @@ This package holds the development files for statically linking leveldb.
 
 %prep
 %setup -q
-%patch0 -p1
 
 %build
+# unfortunately a two-pass build is needed for shared and static libs
 %global _lto_cflags %{_lto_cflags} -ffat-lto-objects
-make %{?_smp_mflags} OPT="%{optflags}"
+%cmake -DBUILD_SHARED_LIBS=ON
+%cmake_build
+cd ..
+%cmake -DBUILD_SHARED_LIBS=OFF
+%cmake_build
 
 %install
-install -d -m 0755 \
-  %{buildroot}%{_includedir} \
-  %{buildroot}%{_libdir} \
-  %{buildroot}%{_bindir}
-
-cp -a \
-  out-static/libleveldb.a   \
-  out-shared/libleveldb.so* \
-  %{buildroot}%{_libdir}
-
-cp -a include/leveldb \
-  %{buildroot}%{_includedir}
-
-cp -a \
-  out-shared/db_bench \
-  %{buildroot}%{_bindir}
+%cmake_install
+# collect shared libs built in the first pass
+cp -a build/libleveldb.so* %{buildroot}%{_libdir}
+# cmake_install omits db_bench
+install -d -m 0755 %{buildroot}%{_bindir}
+cp -a build/db_bench %{buildroot}%{_bindir}
 
 %check
-make %{?_smp_mflags} check
+%ctest
 
 %post   -n %{lib_name} -p /sbin/ldconfig
 %postun -n %{lib_name} -p /sbin/ldconfig
@@ -113,5 +107,6 @@ make %{?_smp_mflags} check
 %files devel-static
 %defattr(-,root,root,-)
 %{_libdir}/libleveldb.a
+%{_libdir}/cmake/
 
 %changelog